MS51
Nov. 28, 2019
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211
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Rev 1.00
MS51
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SE
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CHNICAL RE
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CE MA
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UAL
6.2.2
Power Management
Overview
6.2.2.1
The MS51 has several features that help user to control the power consumption of the device. The
power reduced feature has two option modes: Idle mode and Power-down mode, to save the power
consumption. For a stable current consumption, the state and mode of each pin should be taken care
of. The minimum power consumption can be attained by giving the pin state just the same as the
external pulls for example output 1 if pull-high is used or output 0 if pull-low. If the I/O pin is floating,
user is recommended to leave it as quasi-bidirectional mode. If P2.0 is configured as a input-only pin,
it should have an external pull-up or pull-low, or enable its internal pull-up by setting P30UP (P3UP.0).
PCON
– Power Control
Register
SFR Address
Reset Value
PCON
87H, All pages
POR: 0001_0000b
Others: 000U _0000b
7
6
5
4
3
2
1
0
SMOD
SMOD0
Reserved
POF
GF1
GF0
PD
IDL
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
Bit
Description
1
PD
Power-down mode
Setting this bit puts CPU into Power-down mode. Under this mode, both CPU and peripheral clocks
stop and Program Counter (PC) suspends. It provides the lowest power consumption. After CPU is
woken up from Power-down, this bit will be automatically cleared via hardware and the program
continue executing the interrupt service routine (ISR) of the very interrupt source that woke the
system up before. After return from the ISR, the device continues execution at the instruction, which
follows the instruction that put the system into Power-down mode.
Note that If IDL bit and PD bit are set simultaneously, CPU will enter Power-down mode. Then it
does not go to Idle mode after exiting Power-down.
0
IDL
Idle mode
Setting this bit puts CPU into Idle mode. Under this mode, the CPU clock stops and Program
Counter (PC) suspends but all peripherals keep activated. After CPU is woken up from Idle, this bit
will be automatically cleared via hardware and the program continue executing the ISR of the very
interrupt source that woke the system up before. After return from the ISR, the device continues
execution at the instruction which follows the instruction that put the system into Idle mode.
Idle Mode
6.2.2.2
Idle mode suspends CPU processing by holding the Program Counter. No program code are fetched
and run in Idle mode. It forces the CPU state to be frozen. The Program Counter (PC), Stack Pointer
(SP), Program Status Word (PSW), Accumulator (ACC), and the other registers hold their contents
during Idle mode. The port pins hold the logical states they had at the time Idle was activated.
Generally, it saves considerable power of typical half of the full operating power.
Since the clock provided for peripheral function logic circuit like timer or serial port still remain in Idle
mode, the CPU can be released from the Idle mode with any of enabled interrupt sources. User can
put the device into Idle mode by writing 1 to the bit IDL (PCON.0). The instruction that sets the IDL bit
is the last instruction that will be executed before the device enters Idle mode.
The Idle mode can be terminated in two ways. First, as mentioned, any enabled interrupt will cause an
