ML51/ML54/ML56
Sep. 01, 2020
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Manual
6 FUNCTIONAL DESCRIPTION
6.1 Memory Organization
A standard 80C51 based microcontroller divides the memory into two different sections, Program
Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the
Data Memory is used to store data or variations during the program execution.
The Data Memory occupies a separate address space from Program Memory. In ML51/ML54/ML56
Series, there are 256 bytes of internal scratch-pad RAM. For many applications those need more
internal RAM, the ML51/ML54/ML56 Series provides another on-chip 4 Kbytes of RAM, which is called
XRAM, accessed by MOVX instruction.
The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application
ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG
bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have
different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash
control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O
pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these
modes.
6.1.1
Program Memory
The Program Memory stores the program codes to execute as shown in Figure 6.1-1
ML51/ML54/ML56 Series Program Memory Map. After any reset, the CPU begins execution from
location 0000H.
To service the interrupts, the interrupt service locations (called interrupt vectors) should be located in
the Program Memory. Each interrupt is assigned with a fixed location in the Program Memory. The
interrupt causes the CPU to jump to that location with where it commences execution of the interrupt
service routine (ISR). External Interrupt 0, for example, is assigned to location 0003H. If External
Interrupt 0 is going to be used, its service routine should begin at location 0003H. If the interrupt is not
going to be used, its service location is available as general purpose Program Memory.
The interrupt service locations are spaced at an interval of eight bytes: 0003H for External Interrupt 0,
000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service
routine is short enough (as is often the case in control applications), it can reside entirely within the 8-
Byte interval. However longer service routines should use a JMP instruction to skip over subsequent
interrupt locations if other interrupts are in use.
The ML51/ML54/ML56 Series provides two internal Program Memory blocks APROM and LDROM.
Although they both behave the same as the standard 8051 Program Memory, they play different rules
according to their ROM size. The APROM on ML51/ML54/ML56 Series can be up to 64 Kbytes. User
Code is normally put inside. CPU fetches instructions here for execution. The MOVC instruction can
also read this region.
The other individual Program Memory block is called LDROM. The normal function of LDROM is to
store the Boot Code for ISP. It can update APROM space and CONFIG bytes. The code in APROM
can also re-program LDROM. For ISP details and configuration bit setting related with APROM and
LDROM, see Section 6.3.1.5
“In-System-Programming (ISP)”. Note that APROM and LDROM are
hardware individual blocks, consequently if CPU re-boots from LDROM, CPU will automatically re-
vector Program Counter 0000H to the LDROM start address. Therefore, CPU accounts the LDROM
as an independent Program Memory and all interrupt vectors are independent from APROM.