ML51/ML54/ML56
Sep. 01, 2020
Page
79
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
5 BLOCK DIAGRAM
5.1 ML51/ML54/ML56 Series Full Function Block
1T High
Performance
8051 Core
PWM0/1/2/3
Watchdog Timer
Serial Ports
(UART 0/1)
Timer 0/1
POR / LVR / BOD
I
2
C0/1
I2C0_SDA
I2C0_SCL
V
DD
V
SS
Timer 2 with
Input Capture
FB0
SPI0
12-bit ADC
15
Self Wake-up
Timer
Timer 3
Smart Card/
Series Ports
(UART 2/3)
I2C1_SDA
SPI1
8
-b
it
In
te
rn
a
l B
u
s
AIN0~7, 9~15
STADC
UART2_TXD
UART2_RXD
UART0_RXD
UART0_TXD
UART1_TXD
UART1_RXD
I2C1_SCL
SPI0_MOSI
SPI0_SS
SPI0_SCK
SPI0_MISO
SPI1_MOSI
SPI1_SS
SPI1_SCK
SPI1_MISO
ICAP0~2
T1
T0
6
3
External V
REF
Max. 64KB
APROM Flash
Max. 4KB
LDROM Flash
Max. Bytes
Data Flash
(page: 128B)
Clock Divider
24 MHz Internal
RC Oscillator
(HIRC)
System Clock
38.4 kHz Internal
RC Oscillator
(LIRC)
4-24 MHz
Oscillator Circuit
(HXT)
32768 Hz
Oscillator Circuit
(LXT)
XIN
XOUT
X32IN
X32OUT
Internal V
REF
256 bytes
Internal RAM
P2
P3
P4
P2[7:0]
8
8
P4[7:0]
P1
P1[7:0]
8
P5
P5[7:0]
8
P6
P6[7:0]
8
P3[7:0]
8
Any Port
8
GPIO Interrupt
External Interrupt
INT0
INT1
4 Kbytes XRAM
(Auxiliary RAM)
PDMA with CRC
PWM0CH0~5
UART3_TXD
UART3_RXD
ACMP 0/1
ACMP0_P
ACMP0_N
ACMP1_N
ACMP1_P
Memory
Access
GPIO
Analog
Peripheral
System Clock
Source
Digital
Peripheral
Power
Management
P0
P0[7:0]
8
PWM1/2/3CH0~1
6
RTC
LCD
Touch key
SEG
COM
TK0~14
15
4/6/8
32/30/28
Figure 5.1-1 Functional Block Diagram