Nuvoton NuMicro ML51 Series, Technical Reference Manual, Page: 701 / 719

ML51/ML54/ML56
Sep. 01, 2020 Page 701 of 719 Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
Instruction OPCODE Bytes Clock Cycles
ML51/ML54/ML56 Series VS.
Tradition 80C51 Speed Ratio
AJMP addr11 01, 21, 41, 61, 81, A1,
C1, E1[3]
2 3 8
LJMP addr16 02 3 4 6
SJMP rel 80 2 3 8
JMP @A+DPTR 73 1 3 8
JZ rel 60 2 3 8
JNZ rel 70 2 3 8
JC rel 40 2 3 8
JNC rel 50 2 3 8
JB bit, rel 20 3 5 4.8
JNB bit, rel 30 3 5 4.8
JBC bit, rel 10 3 5 4.8
CJNE A, direct, rel B5 3 5 4.8
CJNE A, #data, rel B4 3 4 6
CJNE Rn, #data, rel B8~BF 3 4 6
CJNE @Ri, #data, rel B6, B7 3 6 4
DJNZ Rn, rel D8~DF 2 4 6
DJNZ direct, rel D5 3 5 4.8
Note:
1. The ML51/ML54/ML56 Series does not have external memory bus. MOVX instructions are used to access internal XRAM.
2. The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be [A10, A9, A8, 1,
0, 0, 0, 1].
3. The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be [A10, A9, A8, 0,
0, 0, 0, 1].
Table 6.20-3 Instruction Set