ML51/ML54/ML56
Sep. 01, 2020
Page
536
of 719
Rev 2.00
ML
51
/ML
54
/ML
5
6 S
E
RI
E
S
TECHNI
CA
L
RE
F
E
R
E
NC
E
M
A
NU
A
L
ML51/M
L54
/M
L56
Series
Tec
hnical Reference
Manual
6.12 Inter-Integrated Circuit (I
2
C)
6.12.1 Overview
The ML51/ML54/ML56 Series provides two Inter-Integrated Circuit (I
2
C) bus to serves as an serial
interface between the microcontrollers and the I
2
C devices such as EEPROM, LCD module,
temperature sensor, and so on. The I
2
C bus used two wires design (a serial data line SDA and a serial
clock line SCL) to transfer information between devices.
The I
2
C bus uses bi-directional data transfer between masters and slaves. There is no central master
and the multi-master system is allowed by arbitration between simultaneously transmitting masters.
The serial clock synchronization allows devices with different bit rates to communicate via one serial
bus. The I
2
C bus supports four transfer modes including master transmitter, master receiver, slave
receiver, and slave transmitter. The I
2
C interface only supports 7-bit addressing mode. A special mode
General Call is also available. The I
2
C can meet both standard (up to 100kbps) and fast (up to 400k
bps) speeds.
6.12.2 Features
2 sets of I
2
C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I
2
C interrupt if the I
2
C bus hangs up and timer-out
counter overflows
Multiple address recognition (four slave addresses with mask option)
Supports hold time programmable
6.12.3 Functional Description
For a bi-directional transfer operation, the SDA and SCL pins should be open-drain pads. This
implements a wired-AND function, which is essential to the operation of the interface. A low level on a
I
2
C bus line is generated when one or more I
2
C devices output a “0”. A high level is generated when
all I
2
C devices output “1”, allowing the pull-up resistors to pull the line high. In ML51, user should set
output latches of SCL and SDA. As logic 1 before enabling the I
2
C function by setting I2CEN.
SDA SCL
Slave Device
SDA SCL
Other MCU
SDA
SCL
V
DD
R
UP
R
UP
SDA SCL
ML56
Figure 6.12-1 I
2
C Bus Interconnection