ML51/ML54/ML56
Sep. 01, 2020
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ML51/M
L54
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L56
Series
Tec
hnical Reference
Manual
Slave Select Pin Configuration
6.11.4.3
The ML51/ML54/ML56 Series SPI gives a flexible
SS
̅̅̅̅̅
pin feature for different system requirements.
When the SPI operates as a Slave,
SS
̅̅̅̅̅
pin always rules as Slave select input. When the Master mode
is enabled,
SS
̅̅̅̅̅
has three different functions according to DISMODF (SPInSR.3) and SSOE
(SPInCR.7). By default, DISMODF is 0. It means that the Mode Fault detection activates.
SS
̅̅̅̅̅
is
configured as a input pin to check if the Mode Fault appears. On the contrary, if DISMODF is 1, Mode
Fault is inactivated and the SSOE bit takes over to control the function of the
SS
̅̅̅̅̅
pin. While SSOE is 1,
it means the Slave select signal will generate automatically to select a Slave device. The
SS
̅̅̅̅̅
as output
pin of the Master usually connects with the
SS
̅̅̅̅̅
input pin of the Slave device. The
SS
̅̅̅̅̅
output
automatically goes low for each transmission when selecting external Slave device and goes high
during each idle state to de-select the Slave device. While SSOE is 0 and DISMODF is 1,
SS
̅̅̅̅̅
is no
more used by the SPI and reverts to be a general purpose I/O pin.
DISMODF
SSOE
Master Mode (MSTR = 1)
Slave Mode (MSTR = 0)
0
X
SS
̅̅̅̅
input for Mode Fault
SS
̅̅̅̅
Input for Slave select
1
0
General purpose I/O
1
1
Automatic
SS
̅̅̅̅
output
Table 6.11-1 Slave Select Pin Configurations
Mode Fault Detection
6.11.4.4
The Mode Fault detection is useful in a system where more than one SPI devices might become
Masters at the same time. It may induce data contention. When the SPI device is configured as a
Master and the
SS
̅̅̅̅̅
input line is configured for Mode Fault input depending on SPInCR0, a Mode Fault
error occurs once the
SS
̅̅̅̅̅
is pulled low by others. It indicates that some other SPI device is trying to
address this Master as if it is a Slave. Instantly the MSTR and SPIEN control bits in the SPInCR are
cleared via hardware to disable SPI, Mode Fault flag MODF (SPInSR.4) is set and an interrupt is
generated if ESPI and EA are enabled.
Write Collision Error
The SPI is signal buffered in the transfer direction and double buffered in the receiving and transmit
direction. New data for transmission cannot be written to the shift register until the previous transaction
is complete. Write collision occurs while SPInDR be written more than once while a transfer was in
progress. SPInDR is double buffered in the transmit direction. Any writing to SPInDR cause data to be
written directly into the SPI shift register. Once a write collision error is generated, WCOL (SPInSR.6)
will be set as 1 via hardware to indicate a write collision. In this case, the current transferring data
continues its transmission. However the new data that caused the collision will be lost. Although the
SPI logic can detect write collisions in both Master and Slave modes, a write collision is normally a
Slave error because a Slave has no indicator when a Master initiates a transfer. During the receiving
of Slave, a write to SPInDR causes a write collision in Slave mode. WCOL flag needs to be cleared via
software.
Overrun Error
For receiving data, the SPI is double buffered in the receiving direction. The received data is
transferred into a parallel read data buffer so the shifter is free to accept a second serial byte.
However, the received data should be read from SPInDR before the next data has been completely
shifted in. As long as the first byte is read out of the read data buffer and SPIF is cleared before the
next byte is ready to be transferred, no overrun error condition occurs. Otherwise the overrun error
occurs. In this condition, the second byte data will not be successfully received into the read data
register and the previous data will remains. If overrun occur, SPIOVF (SPInSR.5) will be set via
hardware. An SPIOVF setting will also require an interrupt if enabled. Figure 6.11-7 SPI Overrun
Waveform shows the relationship between the data receiving and the overrun error.