ML51/ML54/ML56
Sep. 01, 2020
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ML51/M
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L56
Series
Tec
hnical Reference
Manual
6.11.4 Functional Description
SPI block diagram provides an overview of SPI architecture in this device. The main blocks of SPI are
the SPI control register logic, SPI status logic, clock rate control logic, and pin control logic. For a
serial data transfer or receiving, The SPI block exists a shift register and a read data buffer. It is
double buffered in the receiving and transmit directions. Transmit data cannot be written to the shifter
until the previous transfer is complete. Receiving logic consists of parallel read data buffer so the shift
register is free to accept a second data, as the first received data will be transferred to the read data
buffer.
The 2 set, 16 pins of SPI interface and 4 pins of SPI0 interface which are Master-In/Slave-Out (MISO),
Master-Out/Slave-In (MOSI), Shift Clock (SPCLK), and Slave Select (
SS
̅̅̅̅
). The MOSI pin is used to
transfer a 8-bit data in series from the Master to the Slave. Therefore, MOSI is an output pin for
Master device and an input for Slave. Respectively, the MISO is used to receive a serial data from the
Slave to the Master.
The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift
clock is used to synchronize the data movement both in and out of the devices through their MOSI and
MISO pins. The shift clock is driven by the Master mode device for eight clock cycles. Eight clocks
exchange one byte data on the serial lines. For the shift clock is always produced out of the Master
device, the system should never exist more than one device in Master mode for avoiding device
conflict.
Each Slave peripheral is selected by one Slave Select pin (
SS
̅̅̅̅
). The signal should stay low for any
Slave access. When
SS
̅̅̅̅
is driven high, the Slave device will be inactivated. If the system is multi-
slave, there should be only one Slave device selected at the same time. In the Master mode MCU, the
SS
̅̅̅̅
pin does not function and it can be configured as a general purpose I/O. However,
SS
̅̅̅̅
can be used
as Master Mode Fault detection (see Section 6.11.4.4
“Mode Fault Detection”) via software setting if
multi-master environment exists. The ML51/ML54/ML56 Series also provides auto-activating function
to toggle
SS
̅̅̅̅
between each byte-transfer.
MISO
MOSI
SPCLK
SS
I/O
PORT
0
1
2
3
I/O
PORT
0
1
2
3
S
O
S
I
S
C
K
S
S
Slave device 1
Master/Slave
MCU1
MISO
MOSI
SPCLK
SS
Master/Slave
MCU2
S
O
S
I
S
C
K
S
S
Slave device 2
S
O
S
I
S
C
K
S
S
Slave device 3
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection
Figure 6.11-2 shows a typical interconnection of SPI devices. The bus generally connects devices
together through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The
Master devices select the individual Slave devices by using four pins of a parallel port to control the
four
SS
̅̅̅̅
pins. MCU1 and MCU2 play either Master or Slave mode. The
SS
̅̅̅̅
should be configured as
Master Mode Fault detection to avoid multi-master conflict.
