NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
5.8.3 Block Diagram
A
P
B
B
u
s
PA[15:0]
PA[15:0]
Control Register
PB[15:0]
Control Register
PC[14:0]
Control Register
PD[15:0]
Control Register
PE[15:0]
Control Register
PF[15:0]
Control Register
PG[15:0]
Control Register
PH[15:0]
Control Register
PI[15:0]
Control Register
PJ[4:0]
Control Register
De-bounce Control Register
Control Registers
Interrupt,
Wake-up Event
Detector
PB[15:0]
PC[14:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PI[15:0]
PJ[4:0]
PH[15:0]
GPIO_INT
Figure 5.8-1 GPIO Block Diagram
5.8.4 Basic Configuration
Before using GPIO
, it’s necessary to enable clock of GPIO. Set GPIO (CLK_PCLKEN0[4]) high to
enable GPIO
’s clock.
To configure pin Px.n as a General-Purpose I/O, set the corresponding field of register
SYS_GPA_MFPL, SYS_GPA_MFPH, SYS_GPB_MFPL, SYS_GPB_MFPH, SYS_GPC_MFPL,
SYS_GPC_MFPH, SYS_GPD_MFPL, SYS_GPD_MFPH, SYS_GPE_MFPL, SYS_GPE_MFPH,
SYS_GPF_MFPL, SYS_GPF_MFPH, SYS_GPG_MFPL, SYS_GPG_MFPH, SYS_GPH_MFPL,
SYS_GPH_MFPH, SYS_GPI_MFPL, SYS_GPI_MFPH and SYS_GPJ_MFPL to 0.
For example, if user want to configure pin PA.0 as a General-Purpose I/O, it
’s necessary to set
MFP_GPA0 (SYS_GPA_MFPL[3:0]) to 0.
5.8.5 Functional Description
Input mode
5.8.5.1
Set OUTEN (GPIOx_DIR[n]) to 0 as the Px.n pin is in Input mode and the I/O pin is in tri-state (high
impedance) without output drive capability. The DATAIN (GPIOx_DATAIN[n]) value reflects the status
of the corresponding port pins.
Input buffer type is selectable in this mode. By setting ICEN (GPIOx_ICEN[n]) high to enable CMOS
type input buffer while by setting ISEN (GPIOx_ISEN[n]) high to enable Schmitt trigger type input
buffer. By setting both ICEN (GPIOx_ICEN[n]) and ISEN (GPIOx_ISEN[n]) low input buffer disabled.
Setting both ICEN (GPIOx_ICEN[n]) and ISEN (GPIOx_ISEN[n]) high is forbidden.
