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NUC502 

 

 

Apr 30, 2015 

Page 

1

 of 266 

Rev 1.1 

ARM

®

 ARM7TDMI Based 

32-bit Microprocessor

 

 

 

 

 

 

 

NUC502 Series 

User Manual 

 

 

 

 

 

 

 

The information described in this document is the exclusive intellectual property of 

 Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. 

 

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system 

design. Nuvoton assumes no responsibility for errors or omissions. 

All data and specifications are subject to change without notice. 

 

For additional information or questions, please contact: Nuvoton Technology Corporation.  

www.nuvoton.com

 

 
 

 
 

Summary of Contents for NUC502ADN

Page 1: ...gy Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design Nuvoton assumes...

Page 2: ...gisters 29 6 3 Clock Controller 43 6 3 1 Function Description 43 6 3 2 Clock Control Registers 44 6 4 SPI Synchronous Serial Interface Controller Master Mode 56 6 4 1 Overview 56 6 4 2 Features 56 6 4...

Page 3: ...Mapping 112 6 8 6 AIC Control Registers 114 6 9 General Purpose I O 128 6 9 1 Overview and Features 128 6 9 2 GPIO Control Register Mapping 129 6 9 3 GPIO Control Register Description 130 6 10 I2C Syn...

Page 4: ...trol Register Map 211 6 13 5 SPIMS Control Register Description 212 6 14 Timer Controller 218 6 14 1 General Timer Controller 218 6 14 2 Watchdog Timer 218 6 14 3 Timer Control Registers Map 220 6 15...

Page 5: ...NUC502 Apr 30 2015 Page 5 of 266 Rev 1 1 7 3 3 Voice Recorder Characteristic 261 8 Package Specifications 262 9 REVISION HISTORY 265...

Page 6: ...idge games that require large code storage and variation of game play scenarios the patented Extensible XIP Addressing on SpiMemory gives the flexibility whenever program execution speed is not a crit...

Page 7: ...32 segments with address tags SpiMemory interface with code protection DMA mode for code booting from SpiMemory to internal SRAM Direct CPU read access from SpiMemory 128 bit OTP key for code protecti...

Page 8: ...y mode Dedicated LVD LVR 8 level voltage detection Miscellaneous Two programmable 32 bit timers with 8 bit pre scale One 32 bit watch dog timer 32 768KHz RTC function support Up to 26 37 GPIO pins for...

Page 9: ...NUC502 Apr 30 2015 Page 9 of 266 Rev 1 1 3 Pad and Pin Configuration LQFP 48 Pin Out NUC502ADN...

Page 10: ...NUC502 Apr 30 2015 Page 10 of 266 Rev 1 1 LQFP 64 Pin Out NUC502BDN NUC502CDN...

Page 11: ...Default Function For example If the GPA 12 is configured to be SPIMS_SO by PAD_REG1 and it is also configured to be PWMT0 by PAD_REG0 the actual function of GPA 12 would be SPIMS_SO because the SPIMS...

Page 12: ...PIMS_SCK PWMT1 Power on set 48 64 GPA 14 SPIMS_SS Slave USB_DET GPA 15 PWMT2 USB_DET I2C_DATA GPB 0 PWMT3 USB_DET I2C_CLK GPB 1 PWMT0 USB_DET UART0_TXD Power on set ICE GPB 2 PWMT1 USB_DET UART0_RXD G...

Page 13: ...2 Alternative Function 3 Power on setting X12M EX12M X32K EX32K POWER VPP 6 5V VBAT USBVDD33 DVDD33 DVDD33 AVDD33 DVSS DVSS DVSS AVSS VCC_CORE OUTPUT Pin Function for LQFP 64 TCK TMS TDI TDO nTRST GP...

Page 14: ...unction Name Alternative Function 1 Alternative Function 2 Alternative Function 3 Power on setting GPC 5 PWMT2 UART1_TXD GPC 6 PWMT3 UART1_RXD GPC 7 PWMT0 UART1_CTS GPC 8 PWMT1 UART1_RTS GPC 9 PWMT2 I...

Page 15: ...pose input output digital pin AI 5 ADC analog input 5 GPA 6 AI 6 5 4 4 4 8mA I O with Analog input GPA 6 General purpose input output digital pin AI 6 ADC analog input 6 GPA 7 AI 7 LVD 6 5 5 4 8mA I O...

Page 16: ...WM output for timer 2 USB_DET USB detected pin I2C_DATA I2C data input output pin if this pin is select for I2C function GPB 0 PWMT3 USB_DET I2C_CLK 34 25 18 4 8mA I O GPB 0 General purpose input outp...

Page 17: ...aster GPB 6 TMS SPIM1_SO PWMT2 18 14 10 12 16mA I O GPB 6 General purpose input output digital pin TMS JTAG ICE Test Mode Select pin LQFP48 only SPI2_SO Serial data output pin for SPIM1 master PWMT2 P...

Page 18: ...output for timer 0 USB_DET USB detected input GPC 4 PWMT1 USB_DET 60 48 4 8mA I O GPC 4 General purpose input output digital pin PWMT1 PWM output for timer 1 USB_DET USB detected input GPC 5 PWMT2 UA...

Page 19: ...evice signal D XTALI 57 45 35 I Crystal input pin XTALO 58 46 36 O Crystal output pin X32KI 45 35 28 I RTC 32 768KHz crystal input pin X32KO 46 36 29 O RTC 32 768KHz crystal output pin nRESET 8 6 6 I...

Page 20: ...g circuit VBAT 47 37 30 1 8V Power supply for internal RTC circuit VCC_CORE 65 66 51 39 LDO 1 8V output pin VPP 67 52 40 OTP 6 5V VPP pin For OTP write this pin supply is 6 5V for read this pin supply...

Page 21: ...tem Block Diagram 32 768kHz ARM7TD MI 64KB SRAM 1 8V LDO OTP Securit y 37 GPIO s USB Device ADC LDV LVR DAC PA SPI SPI RTC X tal 12MHz 3 3V 3 3 VL DO PW M UAR T I2C TIME R N NU UC C5 50 02 2 Battery U...

Page 22: ...1 1 5 Block Diagram 5 1 System Block Diagram ARM7TDMI RTC TIMER UART x 2 PWM AIC Internal Boot ROM 6KB USB SPIM x 2 PLL USBPHY APU Audio DAC Mono 16 bits DAC ADC 8ch 10b SARADC GPIO SPIMS I2C Interna...

Page 23: ...Bus Block Diagram ARM7TDMI APB Bridge RTC TIMER UART0 UART1 PWM AIC 6K Byte ROM ARM7 WRAPPER USB MISC SPIM PLL CLKCTL USBPHY APU Audio DAC Mono 16 bits DAC ADC 8ch 10b SARADC GPIO SPIMS I2C 64K Byte S...

Page 24: ...The standard 32 bit ARM code 2 16 bit THUMB code The THUMB code is 16 bit instruction set that allows it to increase the code density compare to standard ARM core while retaining most of the ARM perf...

Page 25: ...ace 0x0000_0000 0x0000_7FFF IBR_BA Internal Boot ROM IBR Memory Space IBR_remap 0 0x0000_0000 0x1FFF_FFFF SRAM_BA SRAM Memory Space IBR_remap 1 0x2000_0000 0x3FFF_FFFF SRAM_BA SRAM Memory Space IBR_re...

Page 26: ...egisters 0xB800_7000 0xB800_7FFF PWM_BA PWM Controller Registers 0xB800_8000 0xB800_8FFF RTC_BA Real Time Clock RTC Control Register 0xB800_A000 0xB800_AFFF SPIMS_BA SPI master slave function Controll...

Page 27: ...d in Table 6 2 2 If two or more master modules request to access AHB bus at the same time the higher priority request will get the permission to access AHB bus Table 6 2 2 AHB Bus Priority Order in Fi...

Page 28: ...ecified state when the chip is power up or reset Application board needs to add the proper pull down or pull up resistor for the relative configuration pins Pin Name Descriptions Register Bit Mapping...

Page 29: ...0 PAD_REG0 GCR_BA 0x30 R W PAD function 0x0000_0000 PAD_REG1 GCR_BA 0x34 R W PAD function 0x0000_0000 PAD_REG2 GCR_BA 0x38 R W PAD function 0x0000_0000 GPA_DS GCR_BA 0x74 R W GPIOA pads driving streng...

Page 30: ...pins They can be modified by software programming Register Address R W Description Default Value SPOCR GCR_BA 04 R W System Power On Configuration Register 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved...

Page 31: ...package and GPB 9 5 for ICE connection 1 48 pins package and GPB 9 5 use the normal function 2 0 3 b000 test mode 3 b001 test mode 3 b010 test mode 3 b011 test mode 3 b100 Boot from SRAM 3 b101 Boot f...

Page 32: ...16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved LVR_WARM LVD_EN Bits Descriptions 31 2 Reserved Reserved 1 LVR_WARM Low Voltage Reset Warm Up 0 Disable 1 Low Voltage Reset function...

Page 33: ...GPIO_RS T Reserved SRAM_RS T Reserved 23 22 21 20 19 18 17 16 Reserved APU_RST 15 14 13 12 11 10 9 8 Reserved UDC_RST SPIM_RS T I2C_RST PWM_RS T 7 6 5 4 3 2 1 0 Reserved TMR_RS T Reserved UR1_RST UR0_...

Page 34: ...ST I2C controller Reset 0 Normal operation 1 IP reset 8 PWM_RST PWM controller Reset 0 Normal operation 1 IP reset 7 6 Reserved Reserved 5 TMR_RST Timer and Watch Dog controller Reset 0 Normal operati...

Page 35: ...the Priority of CPU in IRQ or FIQ period It can be used to reduce the interrupt latency in a real time system set this bit the CPU will has the highest AHB priority 0 Disable 1 Enable 3 1 Reserved Res...

Page 36: ...t from GPIOC 10 100 PWM Timer 3 input from GPIOB 7 Others disable PWM Timer 3 input function 28 24 PWM_TMR3_O PWM Timer 3 output pin selection 1 output enable 0 output disable 24 PWM Timer 3 output to...

Page 37: ...8 PWM_TMR1_O PWM Timer 1 output pin selection 1 output enable 0 output disable 8 PWM Timer 1 output to GPIOA 13 9 PWM Timer 1 output to GPIOB 2 10 PWM Timer 1 output to GPIOC 4 11 PWM Timer 1 output...

Page 38: ...ons 31 24 Reserved Reserved 23 16 ADCP_EN ADC pins enable 23 16 represents GPIOA 7 0 respectively 0 disable 1 enable 15 13 Reserved Reserved 12 UART1_MEN UART1 Modem pin enable 0 disable 1 GPIOC 8 7 u...

Page 39: ...PIM1 pins at GPIOB 7 5 2 b10 SPIM1 pins at GPIOC 2 0 2 b11 Unacceptable 2 1 I2CP_EN I2C pin enable 2 b00 disable 2 b01 I2C pins at GPIOA 15 and GPIOB 0 2 b10 I2C pins at GPIOC 10 9 2 b11 Unacceptable...

Page 40: ...om GPB 3 0111 USB connection detect pin from GPB 4 1000 USB connection detect pin from GPB 8 1001 USB connection detect pin from GPB 9 1010 USB connection detect pin from GPC 0 1011 USB connection det...

Page 41: ...n Reset Value GPB_DS GCR_BA 78 R W GPIOB driving strength 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved GPB_DS 9 8 7 6 5 4 3 2 1 0 GPB_DS...

Page 42: ...R W GPIOC driving strength 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved GPC_DS 10 8 7 6 5 4 3 2 1 0 GPC_DS 7 0 Bits Descriptions 31 11 R...

Page 43: ..._CK_EN APB_CK_EN APB_Modules_CK_EN The clock controller implements the power control function include the individually clock on or off control register clock source select and the divided number from...

Page 44: ...BCLK CLK_BA 04 R W AHB Device Clock Enable Control Register 0x0000_0083 APBCLK CLK_BA 08 R W APB Device Clock Enable Control Register 0x0000_0007 CLKSEL CLK_BA 10 R W Clock Source Select Control Regis...

Page 45: ...5 14 13 12 11 10 9 8 Pre Scale 7 0 7 6 5 4 3 2 1 0 Reserved INT_EN INTSTS XIN_CTL XTAL_EN Bits Descriptions 31 24 Reserved Reserved 23 8 Pre Scale Pre Scale counter Assume the crystal is stable after...

Page 46: ...escriptions Crystal to stable 1 Enable the pre scale counter 0 Disable the pre scale assume the crystal is stable 0 XTAL_EN Crystal Oscillator Power Down Control 1 Crystal oscillation enable Normal op...

Page 47: ...erved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved APU_CK_EN 7 6 5 4 3 2 1 0 SPIM_CK_EN USBD_CK_EN Reserved APB_CK_EN CPU_CK_EN Bits Descriptions 31 9 Reserved Reserved 8 APU_CK_EN...

Page 48: ...d ADC_CK_E N SPIMS_CK_E N 7 6 5 4 3 2 1 0 Reserve d I2C_CK_E N PWM_CK_E N UART1_CK_E N UART0_CK_E N RTC_CK_E N WD_CK_EN TIMER_CK_E N Bits Descriptions 31 10 Reserved Reserved 9 ADC_CK_EN Analog Digita...

Page 49: ...o control the APB clock only The RTC engine clock source is from the 32 768 KHz crystal input 0 Disable 1 Enable 1 WD_CK_EN Watch Dog Clock Enable The Watch Dog engine clock source is from the crystal...

Page 50: ...Reserved 15 14 ADC_S ADC clock source select 00 clock source from crystal clock in 01 clock source from divided MPLL clock 1x clock source from divided MPLL clock 2 13 8 Reserved Reserved 7 6 UART_S U...

Page 51: ...266 Rev 1 1 Bits Descriptions 1 0 HCLK_S HCLK clock source select 1 0 00 clock source from crystal clock in 01 clock source from divided MPLL clock 10 clock source from divided MPLL clock 2 11 clock...

Page 52: ...19 16 UART_N UART clock divide number from UART clock source The UART clock frequency UART clock source frequency UART_N 1 15 8 APU_N APU clock divide number from APU clock source The APU clock frequ...

Page 53: ...13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Descriptions 31 24 Reserved Reserved 23 16 ADC_N ADC engine clock divide number from ADC clock source The ADC engine clock frequency ADC engine...

Page 54: ...19 18 17 16 Reserved OE BP PD 15 14 13 12 11 10 9 8 OUT_DV IN_DV FB_DV 7 6 5 4 3 2 1 0 FB_DV Bits Descriptions 31 19 Reserved Reserved 18 OE PLL OE FOUT enable pin Control 0 PLL FOUT enable 1 PLL FOUT...

Page 55: ...erred is 250 500 200 FCO MHz MHz NR NF FIN FCO MHz FOUT Output Clock Frequency FIN Input Reference Clock Frequency NR Input Divider 2 x IN_DV 2 NF Feedback Divider 2 x FB_DV 2 NO OUT_DV 00 NO 1 OUT_DV...

Page 56: ...riting a divisor into DIVIDER register can program the frequency of serial clock output to peripherals This controller contains four 32 bit transmit receive buffers and can provide 1 to 4 burst mode o...

Page 57: ...in a transfer Chip select signal is active low You should do following actions basically you should refer to the specification of device for the detailed steps 1 Write a divisor into DIVIDER to determ...

Page 58: ...in SPI_ADDR peripheral address 4 Set SSR register to select spi slave no support ASS in dma mode 5 Set the READ command 03 and 3 Byte SPI Start Address into Tx0 Tx1 Tx2 Tx3 6 Set SPI_CNTRL 0x1a1345 fo...

Page 59: ...DIS_M high disable flash data read CNTRL F_DRD low set sleep interval to 1 CNTRL SLEEP 4 h1 and set SPI flash read command CNTRL SPI_MODE 0x03 0x0b or 0x3b Then users can access SPI flash as a ROM mod...

Page 60: ...SPI_BA 0x14 R Data Receive Register 1 0x0000_0000 Rx2 SPI_BA 0x18 R Data Receive Register 2 0x0000_0000 Rx3 SPI_BA 0x1C R Data Receive Register 3 0x0000_0000 Tx0 SPI_BA 0x20 R W Data Transmit Registe...

Page 61: ...y LSB Tx_NUM 7 6 5 4 3 2 1 0 Tx_BIT_LEN Tx_NEG Rx_NEG GO_BUSY Bits Descriptions 31 24 SPIM_MODE SPI read mode selection 8 h03 standard read mode 8 h0b fast read mode 8 h3b fast read dual output mode 2...

Page 62: ...peration when BOOT_SPI high NOTE When want to access SPI flash through direct memory mapping please set this bit LOW 18 F_TYPE Flash Type 0 SST 16Mbit SPI Serial Flash ST25VF016B 1 PMC 512Kbit Serial...

Page 63: ...s bit is used to insert a dummy phase in SPI flash fast dual read fast read mode when in DMA mode 10 LSB Send LSB First 0 The MSB is transmitted received first which bit in TxX RxX register that is de...

Page 64: ...Transmit On Negative Edge Read Only 1 b1 This module only supports transmitting on negative edge 1 Rx_NEG Receive On Negative Edge Read Only 1 b0 This module only supports receiving on positive edge 0...

Page 65: ...er to adjust the spi_sclki clock input delay There are total 8 buffers in this delay path The actual delay value depends on process 000 one buffer delay 111 8 buffer delay 19 16 IDLE_CNT The idle inte...

Page 66: ...NUC502 Apr 30 2015 Page 66 of 266 Rev 1 1 Bits Descriptions NOTE When set DIVIDER to zero SPI clock will be equal to engine clock NOTE when set DIVIER to zero sleep CNTRL SLEEP can t set to zero...

Page 67: ...ignals are asserted and de asserted by setting and clearing related bits in SSR register 1 If this bit is set spi_ss_o signals are generated automatically It means that device slave select signal whic...

Page 68: ...any bit location of this field will select appropriate spi_ss_o line to be automatically driven to active state for the duration of the transmit receive and will be driven to inactive state for the r...

Page 69: ...3 SPIM_BA 0x1C R Data Receive Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Rx 31 24 23 22 21 20 19 18 17 16 Rx 23 16 15 14 13 12 11 10 9 8 Rx 15 8 7 6 5 4 3 2 1 0 Rx 7 0 Bits Descriptions 31 0 Rx Da...

Page 70: ...18 17 16 Tx 23 16 15 14 13 12 11 10 9 8 Tx 15 8 7 6 5 4 3 2 1 0 Tx 7 0 Bits Descriptions 31 0 Tx Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfe...

Page 71: ...Code Length Register CODE_LEN Register Address R W C Description Reset Value CODE_LEN SPIM_BA 0x34 R W Code length Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CODE_L...

Page 72: ...SPIM_ADDR 15 14 13 12 11 10 9 8 SPIM_ADDR 7 6 5 4 3 2 1 0 SPIM_ADDR Reserved Bits Descriptions 31 24 Reserved Reserved 23 2 SPIM_ADDR SPI Flash start access address Note SPI Flash starting address mus...

Page 73: ...Register Bank AHB Slave interface on AHB A bridge that CPU control and observe the state of APU 6 5 2 3 Buffer Interface and Timer AHB Master interface on AHB Read Audio PCM data from global RAM Buil...

Page 74: ...nd then set it to 0 again This action will reset internal buffers and registers Remember to do this step before you start to run APU 4 Start APU Set bit 0 of APUCON register to 1 This makes APU start...

Page 75: ...00 R W APU Control Register 0x0000_0000 Bits Descriptions 31 17 Reserved Reserved 16 APURST APU Reset 0 No action 1 Reset the whole ADC except register value 15 1 Reserved Reserved 0 APURUN APU Run 0...

Page 76: ...erved Reserved 25 ZERO_EN Zero cross detection enable 0 Disable 1 Enable 24 Reserved Reserved Fix 0 23 17 Reserved Reserved 16 SWAP PCM data format 0 MSB is sample data 2 LSB is sample data 1 1 MSB is...

Page 77: ...PDCON APU_BA 0x08 R W Power Down Control Register 0x0001_0000 Bits Descriptions 31 17 Reserved Reserved 16 ANA_PD Audio DAC Power Down 0 Normal operation 1 Power down 15 0 Reserved Reserved 31 30 29 2...

Page 78: ...0 Disable 1 Enable 16 T1INTEN Threshold 1 Interrupt Enable 0 Disable 1 Enable 15 2 Reserved Reserved 1 T2INTS Threshold 2 Interrupt Status APU fetch data from Threshold 2 complete Write 0 to clear it...

Page 79: ...Address R W Description Reset Value RAMBSAD APU_BA 0x10 R W RAM Base Address Register 0x0000_0000 Bits Descriptions 31 0 BSAD Global RAM Base Address 31 30 29 28 27 26 25 24 BSAD 31 24 23 22 21 20 19...

Page 80: ...ister Address R W Description Reset Value THAD1 APU_BA 0x14 R W Threshold 1 Address Register 0x0000_0000 Bits Descriptions 31 0 TH1 Threshold 1 Address 31 30 29 28 27 26 25 24 TH1 31 24 23 22 21 20 19...

Page 81: ...THAD2 APU_BA 0x18 R W Threshold 2 Address Register 0x0000_0000 Bits Descriptions 31 0 TH2 Threshold 2 Address InternalSRAM 0x00000000 RAM Base Address Threshold 1 Address Threshold 2 Address 31 30 29...

Page 82: ...W Description Reset Value CURAD APU_BA 0x1C R Current Access RAM Address Register 0x0000_0000 Bits Descriptions 31 0 CURAD Current APU Access RAM Address 31 30 29 28 27 26 25 24 CURAD 31 24 23 22 21...

Page 83: ...ndomly mapped to any 2KB space of 0x0000_0000 0x1FFF_FFFF of system memory by modifying the control register Each 2KB memory block could also be disabled individually by modifying control register By...

Page 84: ...er is depicted as following AHB Slave Wrapper I O Decoder TAG Control Register SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM6 SRAM7 SRAM5 SRAM8 SRAM9 SRAM10 SRAM11 SRAM12 SRAM14 SRAM15 SRAM13 SRAM16 SRAM17 SRAM1...

Page 85: ...NUC502 Apr 30 2015 Page 85 of 266 Rev 1 1 6 6 4SRAM System Diagram The following diagram briefs the related circuit with SRAM Controller SRAM Controller Clock Controller Reset Controller AHB Bus...

Page 86: ...each memory block is 2KB Each memory block could be randomly mapped to any 2KB space of 0x0000_0000 0x1FFF_FFFF of system memory For this purpose 32 tag registers are implemented to keep the base addr...

Page 87: ...M Control Register 8 0x0000_4001 SCTRL9 SRAMCTRL_BA 024 R W SRAM Control Register 9 0x0000_4801 SCTRL10 SRAMCTRL_BA 028 R W SRAM Control Register 10 0x0000_5001 SCTRL11 SRAMCTRL_BA 02C R W SRAM Contro...

Page 88: ...SRAMCTRL_BA 064 R W SRAM Control Register 25 0x0000_C801 SCTRL26 SRAMCTRL_BA 068 R W SRAM Control Register 26 0x0000_D001 SCTRL27 SRAMCTRL_BA 06C R W SRAM Control Register 27 0x0000_D801 SCTRL28 SRAM...

Page 89: ...AM Control Register 12 0x0000_6001 SCTRL13 SRAMCTRL_BA 0x034 R W SRAM Control Register 13 0x0000_6801 SCTRL14 SRAMCTRL_BA 0x038 R W SRAM Control Register 14 0x0000_7001 SCTRL15 SRAMCTRL_BA 0x03C R W S...

Page 90: ...erved Reserved 28 11 TAG TAG Address This field keeps the base address of each 2KB memory block Once the address bits 28 11 from system bus are the same with the content of this filed and the VALID fl...

Page 91: ...6 configurable endpoints These endpoints could be configured as IN OUT or ISO state on CFGx 6 4 and the endpoint number can be set on CFGx 3 0 The transmit length in each endpoint is defined in MXPLD...

Page 92: ...pt and Isochronous transfer are implemented in it 6 7 3 3 Digital Phase Lock Loop The bit rate of USB data is 12MHz The DPLL use the 48MHz which comes from the clock control to lock the input data RXD...

Page 93: ...USB event on the bus and a user can read SFR STSX and EPTF to acknowledge what kind of request is to which endpoint and take necessary responses Same as USB interrupt BUS interrupt notifies users of s...

Page 94: ..._BA 0x048 R W Configuration of endpoint 2 0x0000_0000 CFGP2 USB_BA 0x04C R W stall control register and In out ready clear flag of endpoint 2 0x0000_0000 BUFSEG3 USB_BA 0x050 R W Buffer Segmentation o...

Page 95: ...INNAKEN Reserved WAKEFUEN 7 6 5 4 3 2 1 0 Reserved WAKEUPEN FLDEN USBEN BUSEN Bits Descriptions 31 16 Reserved Reserved 15 INNAKEN 0 Disable IN NAK INT Write Only 1 Enable 14 9 Reserved Reserved 8 WAK...

Page 96: ...X 17 15 to know which kind of USB event was occurred cleared by read register STS or write 1 to EVF 21 20 EPTF4 1 USB event occurred check STSX 14 12 to know which kind of USB event was occurred clear...

Page 97: ...o know which kind of bus event was occurred cleared by write 1 to EVF 0 Function Address Register FADDR A seven bit value uses as the address of a device on the USB BUS Register Address R W Descriptio...

Page 98: ...erved Reserved 25 23 STS5 System states of endpoint 5 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end 22 20 STS4 System states of endpoint 4 000 In ACK...

Page 99: ...STS0 System states of endpoint 0 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end 7 Overrun Out Data more than Max Payload or Setup Data more than 8 Byte...

Page 100: ...Disable USB 1 Enable 6 Reserved Reserved 5 RWakeUp 0 Nothing 1 force USB bus to K state used for remote wake up 4 enPHY 0 Disable PHY 1 Enable 3 Timeout No response more than 18 bits time Read Only 2...

Page 101: ...10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FLODET Bits Descriptions 31 1 Reserved Reserved 0 FLODET 0 floating 1 connected Buffer Segmentation Register BUFSEG For Setup token only Register Address R W...

Page 102: ...t 1 0x0000_0000 BUFSEG2 USB_BA 0x040 R W Buffer segmentation of endpoint 2 0x0000_0000 BUFSEG3 USB_BA 0x050 R W Buffer segmentation of endpoint 3 0x0000_0000 BUFSEG4 USB_BA 0x060 R W Buffer segmentati...

Page 103: ...l Payload of endpoint 4 0x0000_0000 MXPLD5 USB_BA 0x074 R W Maximal Payload of endpoint 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7...

Page 104: ...ation of Endpoint 4 0x0000_0000 CFG5 USB_BA 0x078 R W Configuration of Endpoint 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved stall_ctl...

Page 105: ...CFGP 3 USB_BA 0x05C R W stall control register and In out ready clear flag of endpoint 3 0x0000_0000 CFGP 4 USB_BA 0x06C R W stall control register and In out ready clear flag of endpoint 4 0x0000_000...

Page 106: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SE0 Bits Descriptions 31 1 Reserved Reserved 0 SE0 0 Normal state 1 SE0 state In SE0 state the U...

Page 107: ...interrupt source during power on initialization otherwise the system shall behave unexpectedly Within each priority level interrupt source that is positioned in a lower channel has a higher priority I...

Page 108: ...31 24 Audio Processing Unit Interrupt Low 8 Reserved Reserved Reserved Low 9 Reserved Reserved Reserved Low 10 INT_ADC SCR3 23 16 AD Converter Interrupt Low 11 INT_RTC SCR3 31 24 RTC Interrupt Low 12...

Page 109: ...I Master Slave Serial Interface Interrupt Low 28 Reserved Reserved Reserved Low 29 INT_PWR SCR8 15 8 System Wake Up Interrupt Low 30 INT_SPIM SCR8 23 16 SPIM0 1 Interrupt Low 31 Reserved Reserved Rese...

Page 110: ...errupt occurs while an interrupt already exits there are two possible outcomes depending on whether the AIC_IPER has been read If the processor has already read the AIC_IPER and caused the NIRQ line t...

Page 111: ...ority level is not updated in this situation Hence the AIC_EOSCR shouldn t be written ICE Debug Mode This mode allows reading of the AIC_IPER without performing the associated automatic operations Thi...

Page 112: ...s mode will run correctly in normal mode without modification However in normal mode writing to AIC_IPER has no effect and can be removed to optimize the code 6 8 5AIC Registers Mapping Register Addre...

Page 113: ...0x0000_0000 AIC_OISR AIC_BA 118 R Output Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Undefined AIC_MECR AIC_BA 120 W Mask Enable Command Register Undefined AIC_MDCR AIC_BA 124 W M...

Page 114: ...annel 2 Reserved PRIORITY Channel 2 15 14 13 12 11 10 9 8 TYPE Channel 1 Reserved PRIORITY Channel 1 7 6 5 4 3 2 1 0 TYPE channel 0 Reserved PRIORITY Channel 0 Bits Descriptions 31 30 23 22 15 14 7 6...

Page 115: ...the highest priority and the level 7 indicates the lowest priority An interrupt is treated as a FIQ mode for the priority level 0 and is treated as an IRQ mode for other levels If two or more interru...

Page 116: ...30 29 28 27 26 25 24 IRS 31 24 23 22 21 20 19 18 17 16 IRS 23 16 15 14 13 12 11 10 9 8 IRS 15 8 7 6 5 4 3 2 1 0 IRS 7 0 This register records the intrinsic state within each interrupt channel Bits De...

Page 117: ...S 23 16 15 14 13 12 11 10 9 8 IAS 15 8 7 6 5 4 3 2 1 0 IAS 7 0 This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the correspondin...

Page 118: ...1 10 9 8 ISR 15 8 7 6 5 4 3 2 1 0 ISR 7 0 This register identifies those interrupt channels whose are both active and enabled Bits Descriptions 31 0 ISRx Interrupt Status Register Indicates the status...

Page 119: ...ighest priority If the representing interrupt channel possesses a priority level 0 then the interrupt asserted is FIQ mode otherwise it is IRQ mode The value of VECTOR is copied to the register AIC_IS...

Page 120: ...00 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved IRQID The purpose of this register is to record the interrupt channel numbe...

Page 121: ...3 2 1 0 IM 7 0 Bits Descriptions 31 0 IMx Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled Every interrupt channel can be active no matter whether...

Page 122: ...rved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved IRQ FIQ The AIC classifies the interrupt into FIQ mode and IRQ mode This register indicates whether the asserted interrupt is NFIQ or NIRQ...

Page 123: ...ription Reset Value AIC_MECR AIC_BA 120 W Mask Enable Command Register Undefined 31 30 29 28 27 26 25 24 MEC 31 24 23 22 21 20 19 18 17 16 MEC 23 16 15 14 13 12 11 10 9 8 MEC 15 8 7 6 5 4 3 2 1 0 MEC...

Page 124: ...iption Reset Value AIC_MDCR AIC_BA 124 W Mask Disable Command Register Undefined 31 30 29 28 27 26 25 24 MDC 31 24 23 22 21 20 19 18 17 16 MDC 23 16 15 14 13 12 11 10 9 8 MDC 15 8 7 6 5 4 3 2 1 0 MDC...

Page 125: ...31 24 23 22 21 20 19 18 17 16 SSC 23 16 15 14 13 12 11 10 9 8 SSC 15 8 7 6 5 4 3 2 1 0 SSC 7 0 When the NUC502 is under debugging or verification software can activate any interrupt channel by setting...

Page 126: ...1 24 23 22 21 20 19 18 17 16 SCC 23 16 15 14 13 12 11 10 9 8 SCC 15 8 7 6 5 4 3 2 1 0 SCC 7 0 When the NUC502 is under debugging or verification software can deactivate any interrupt channel by settin...

Page 127: ...End of Service Command Register Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This register is used by the interrupt service routine to indicate that...

Page 128: ...pins package and COB of General Purpose I O are shared with special feature functions Supported Features of these I O are input or output facilities pull up resistors All these general purpose I O fun...

Page 129: ...GPIOC_DOUT GP_BA 0x28 R W GPIO Port C Data Output Value 0x0000_0000 GPIOC_PIN GP_BA 0x2C R GPIO Port C Pin Value 0xXXXX_XXXX DBNCECON GP_BA 0x70 R W External Interrupt De bounce Control 0x0000_0000 IR...

Page 130: ...set Value GPIOB_OMD GP_BA 0x10 R W GPIO Port B Bit Output Mode Enable 0x0000_0000 GPIO Port C Bit Output Mode Enable GPIOC_OMD 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 1...

Page 131: ...d 15 14 13 12 11 10 9 8 Reserved OMD10 OMD9 OMD8 7 6 5 4 3 2 1 0 OMD7 OMD6 OMD5 OMD4 OMD3 OMD2 OMD1 OMD0 Bits Descriptions n OMDn Bit Output Mode Enable 1 GPIO port A B C bit n output mode is enabled...

Page 132: ...14 13 12 11 10 9 8 PUEN15 PUEN14 PUEN13 PUEN12 PUEN11 PUEN10 PUEN9 PUEN8 7 6 5 4 3 2 1 0 PUEN7 PUEN6 PUEN5 PUEN4 PUEN3 PUEN2 PUEN1 PUEN0 Register Address R W Description Reset Value GPIOB_PUEN GP_BA 0...

Page 133: ...14 13 12 11 10 9 8 Reserved PUEN10 PUEN9 PUEN8 7 6 5 4 3 2 1 0 PUEN7 PUEN6 PUEN5 PUEN4 PUEN3 PUEN2 PUEN1 PUEN0 Bits Descriptions n PUENn PUEN n Bit Pull up Resistor Enable 1 GPIO port A B C bit n pul...

Page 134: ...000_0000 GPIO Port C Data Output Value GPIOC_DOUT Register Address R W Description Reset Value GPIOC_DOUT GP_BA 0x28 R W GPIO Port C Data Output Value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 2...

Page 135: ...GPIOA_PIN GP_BA 0x0C R GPIO Port A Pin Value 0x0000_XXXX GPIO Port B Pin Value GPIOB_PIN Register Address R W Description Reset Value GPIOB_PIN GP_BA 0x1C R GPIO Port B Pin Value 0x0000_0XXX 31 30 29...

Page 136: ...t Value GPIOC_PIN GP_BA 0x2C R GPIO Port C Pin Value 0x0000_0XXX Reserved 15 14 13 12 11 10 9 8 Reserved PIN 9 8 7 6 5 4 3 2 1 0 PIN 7 0 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserv...

Page 137: ...64 APB clocks 7 Sample interrupt input once per 128 APB clocks 8 Sample interrupt input once per 256 APB clocks 9 Sample interrupt input once per 2 256 APB clocks 10 Sample interrupt input once per 4...

Page 138: ...Where x 0 15 GPAxSEL 0 GPAx pin is grouped as one of interrupt sources to IRQ0 1 GPAx pin is grouped as one of interrupt sources to IRQ1 2 GPAx pin is grouped as one of interrupt sources to IRQ2 3 GP...

Page 139: ...in is grouped as one of interrupt sources to IRQ3 Register Address R W Description Reset Value IRQSRCGPB GP_BA 0x84 R W GPIO Port B IRQ Source Grouping 0x0005_5555 31 30 29 28 27 26 25 24 Reserved 23...

Page 140: ...pin is grouped as one of interrupt sources to IRQ3 Register Address R W Description Reset Value IRQSRCGPC GP_BA 0x88 R W GPIO Port C IRQ Source Grouping 0x002A_AAAA 31 30 29 28 27 26 25 24 Reserved 23...

Page 141: ...up source if both edges are set the high level will be set as wake up level Register Address R W Description Reset Value IRQENGPA GP_BA 0x90 R W GPIO Port A Interrupt Enable 0x0000_0000 31 30 29 28 2...

Page 142: ...NOTE3 When use a pin as power down wake up source if both edges are set the high level will be set as wake up level Register Address R W Description Reset Value IRQENGPB GP_BA 0x94 R W GPIO Port B Int...

Page 143: ...en use a pin as power down wake up source if both edges are set the high level will be set as wake up level Register Address R W Description Reset Value IRQENGPC GP_BA 0x98 R W GPIO Port C Interrupt E...

Page 144: ...Bits Descriptions 31 9 Reserved Reserved 8 IRQ_SRCC Interrupt Request Source Control 0 While the gpio interrupt occur the gpio interrupt controller generate one clock pulse to the AIC 1 While the gpio...

Page 145: ...PA15LHV PA14LHV PA13LHV PA12LHV PA11LHV PA10LHV PA9LHV PA8LHV 7 6 5 4 3 2 1 0 PA7LHV PA6LHV PA5LHV PA4LHV PA3LHV PA2LHV PA1LHV PA0LHV Where x 0 15 Register Address R W Description Reset Value IRQLHGPA...

Page 146: ...scriptions x PCxLHV Latched value of GPCx while the IRQ IRQ0 IRQ3 selected by IRQLHSEL is active Where x 0 15 NOTE When a latched pin value is 0 there will be 2 meanings either the pin s input is reco...

Page 147: ...TG PA0TG Where x 0 15 NOTE The trigger source will be latched when the corresponding rising or falling trigger enable is setup and the pin state toggle is recognized through de bounce or without de bo...

Page 148: ...ng trigger enable is setup and the pin state toggle is recognized through de bounce or without de bounce no matter whether the source is an input or output pin Other NOTE for related setup NOTE1 For t...

Page 149: ...it with the MSB being transmitted first An acknowledge bit follows each transferred byte Each bit is sampled during the high period of SCL therefore the SDA line may be changed only during the low per...

Page 150: ...a 7 bit address The transfer direction is not changed 1 read data transfer n bytes acknowledge S SLAVE ADDRESS R W A DATA A DATA A P A master reads a slave immediately after the first byte address ST...

Page 151: ...irection No two slaves in the system can have the same address Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the...

Page 152: ...fer is done the I2C_TIP flag is cleared the IF the flag set if enabled then an interrupt generated The Receive Register RxR contains valid data after the IF flag has been set The software may issue a...

Page 153: ...STOP bit Wait for interrupt or I2C_TIP flag to negate SCL SDA S W ACK First command sequence ACK P Second command sequence NOTE Please note that the time for the Interrupt Service Routine is not shown...

Page 154: ...TART bit set WRITE bit Wait for interrupt or I2C_TIP flag to negate 8 Read I2C_RxACK bit from CSR Register it should be 0 9 Set READ bit set ACK to 1 NACK set STOP bit 10 Read out received data from R...

Page 155: ...0 1 1 Pin SCL_PADOEN_O SDA_PADOEN_O SDO_PADOEN_O The other two registers SCW and SDW just represent the status of input port scl pin sda pin Software can read write this register at any time but the o...

Page 156: ...00 R W Control and Status Register 0x0000_0000 DIVIDER I2C_BA 0x04 R W Clock Pre scale Register 0x0000_0000 CMDR I2C_BA 0x08 R W Command Register 0x0000_0000 SWR I2C_BA 0x0C R W Software Mode Control...

Page 157: ...he I2 C core lost arbitration Arbitration is lost when A STOP signal is detected but no requested The master drives SDA high but SDA is low 8 I2C_TIP Transfer In Progress Read only 0 Transfer complete...

Page 158: ...in multi byte transmit mode Arbitration is lost NOTE This bit is read only but can be cleared by writing 1 to this bit 1 IE Interrupt Enable 0 Disable I2 C Interrupt 1 Enable I2 C Interrupt 0 I2C_EN I...

Page 159: ...8 7 6 5 4 3 2 1 0 DIVIDER 7 0 Bits Descriptions 31 16 Reserved Reserved 15 0 DIVIDER Clock Pre scale Register It is used to pre scale the SCL clock line Due to the structure of the I2 C interface the...

Page 160: ...Reserved Reserved 4 START Generate Start Condition Generate repeated start condition on I2 C bus when this bit set 1 3 STOP Generate Stop Condition Generate stop condition on I2 C bus when this bit se...

Page 161: ...o matter I2C_EN is 0 or 1 But SCL and SDA are controlled by software only when I2C_EN 0 Bits Descriptions 31 6 Reserved Reserved 5 SER Serial Interface SDO Status Read only 0 SDO is Low 1 SDO is High...

Page 162: ...ta Receive Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Rx 7 0 Bits Descriptions 31 8 Reserved Reserved 7 0 Rx...

Page 163: ...The I2 C core used 32 bit transmit buffer and provide multi byte transmit function Set CSR Tx_NUM to a value that you want to transmit I2 C core will always issue a transfer from the highest byte firs...

Page 164: ...n feel free to write data to counter buffer register and comparator buffer register without generating glitch When 16 bit down counter reaches zero the interrupt request is generated to inform CPU tha...

Page 165: ...the same time 6 11 2 Features Two 8 bit pre scales and Two clock dividers Four clock selectors Four 16 bit counters and four 16 bit comparators Two Dead Zone generator Capture function 6 11 3 PWM Tim...

Page 166: ...15 or GPB 3 or GPB 6 or GPC 5 or GPC 9 PWM_OE 3 enable timer PWM3 output GPB 0 or GPB 4 or GPB 7 or GPC 6 or GPC 10 timer output GPIO pin select by PAD Control register PAD_REG0 The following figure...

Page 167: ...NUC502 Apr 30 2015 Page 167 of 266 Rev 1 1 8 bit Pre scale CP1 Control Logic Dead Zone Generator 1 1 2 1 4 1 8 1 16 Control Logic CNR2 CMR2 CNR3 CMR3 pwm_clk PWM2 PWM3 Dead Zone Dead Zone DZI0...

Page 168: ...ng function enabling the reload value changed for next timer operation without stopping current timer operation Although new timer value is set current timer operation still operate successfully The c...

Page 169: ...NT 150 Reg_CMP 50 151 51 200 50 Reg_CNT 199 Reg_CMP 49 Reg_CNT 99 Reg_CMP 0 100 1 Reg_CNT 0 Reg_CMP XX Stop PWM double buffering PWM Double Buffering Illustration 6 11 7 Modulate Duty Ratio The double...

Page 170: ...1 PWM cycle 151 101 51 1 PWM Controller Output Duty Ratio 6 11 8 Dead Zone Generator PWM is implemented with Dead Zone generator They are built for power device protection This function enables genera...

Page 171: ...oggle mode one shot mode and PWM timer off PCR 4 Setup the comparator register CMR 5 Setup the counter register CNR 6 Setup the interrupt enable register PIER 7 Setup PWM output enables POE 8 Enable P...

Page 172: ...CR 4 Setup the comparator register CMR 5 Setup the counter register CNR 6 Setup the capture register CCR 7 Setup PWM output enables POE 8 Enable PWM timer PCR 6 11 10 2 Capture Basic Timer Operation A...

Page 173: ...4 R W PWM Comparator Register 3 0x0000_0000 PDR3 PWM_BA 0x038 R PWM Data Register 3 0x0000_0000 PIER PWM_BA 0x040 R W PWM Interrupt Enable Register 0x0000_0000 PIIR PWM_BA 0x044 R C PWM Interrupt Indi...

Page 174: ...ength is received from clock selector 1 23 16 DZI0 Dead zone interval register 0 These 8 bit determine dead zone length The 1 unit time of dead zone length is received from clock selector 0 15 8 CP1 C...

Page 175: ...scriptions 31 15 Reserved Reserved 14 12 CSR3 Timer 3 Clock Source Selection Select clock input for timer 3 CSR3 14 12 Input clock divided by 100 1 011 16 010 8 001 4 000 2 11 Reserved Reserved 10 8 C...

Page 176: ...eserved Reserved 27 CH3MOD Timer 3 Toggle One Shot Mode 1 Toggle Mode 0 One Shot Mode NOTE If there is a rising transition at this bit it will cause CNR3 and CMR3 be clear 26 CH3INV Timer 3 Inverter O...

Page 177: ...Reserved 8 CH1EN Timer 1 Enable Disable 1 Enable 0 Disable 7 6 Reserved Reserved 5 DZEN1 Dead Zone 1 Generator Enable Disable 1 Enable 0 Disable 4 DZEN0 Dead Zone 0 Generator Enable Disable 1 Enable...

Page 178: ...PWM_BA 0x030 R W PWM Counter Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNR 15 8 7 6 5 4 3 2 1 0 CNR 7 0 Bits Descriptions 31 16 Res...

Page 179: ...27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMR 15 8 7 6 5 4 3 2 1 0 CMR 7 0 Bits Descriptions 31 16 Reserved Reserved 15 0 CMR PWM Comparator Register Inserted data r...

Page 180: ...WM Data Register 1 0x0000_0000 PDR2 PWM_BA 0x02C R PWM Data Register 1 0x0000_0000 PDR3 PWM_BA 0x038 R PWM Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved...

Page 181: ...27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PIER3 PIER2 PIER1 PIER0 Bits Descriptions 31 4 Reserved Reserved 3 PIER3 PWM Timer 3 Inter...

Page 182: ...rved 7 6 5 4 3 2 1 0 Reserved PIIR3 PIIR2 PIIR1 PIIR0 Bits Descriptions 31 4 Reserved Reserved 3 PIIR3 PWM Timer 3 Interrupt Flag 1 Interrupt Flag ON 0 Interrupt Flag OFF 2 PIIR2 PWM Timer 2 Interrupt...

Page 183: ...nd this bit was 1 22 CRLRD1 CRLR1 dirty bit When input channel 1 has a falling transition CRLR1 was updated and this bit was 1 21 Reserved Reserved 19 CAPCH1EN Capture Channel 1 transition Enable Disa...

Page 184: ...disable Channel 0 Interrupt 2 FL IE0 Channel 0 Falling Interrupt Enable ON OFF 1 Enable 0 Disable When Enable if Capture detects Channel 0 has falling transition Capture issues an Interrupt 1 RL IE0 C...

Page 185: ...0 Disable When Enable Capture latched the PMW counter and saved to CRLR Rising latch and CFLR Falling latch When Disable Capture does not update CRLR and CFLR and disable Channel 3 Interrupt 18 FL IE...

Page 186: ...rrupt 2 FL IE2 Channel 2 Falling Interrupt Enable ON OFF 1 Enable 0 Disable When Enable if Capture detects Channel 2 has falling transition Capture issues an Interrupt 1 RL IE2 Channel 2 Rising Interr...

Page 187: ...tch Register channel 0 0x0000_0000 CFLR1 PWM_BA 0x064 R W Capture Falling Latch Register channel 1 0x0000_0000 CFLR2 PWM_BA 0x06C R W Capture Falling Latch Register channel 2 0x0000_0000 CFLR3 PWM_BA...

Page 188: ...the same time 0 OFF 1 ON CAPENR 3 0 3210 xxx1 Capture channel 0 is from GPA_DIN 12 or GPB_DIN 1 or GPB_DIN 8 or GPC_DIN 3 or GPC_DIN 7 xx1x Capture channel 1 is from GPA_DIN 13 or GPB_DIN 2 or GPB_DIN...

Page 189: ...M1 PWM0 Bits Descriptions 31 4 Reserved Reserved 3 PWM3 PWM timer 3 Output Enable Setup 1 Enable 0 Disable 2 PWM2 PWM timer 2 Output Enable Setup 1 Enable 0 Disable 1 PWM1 PWM timer 1 Output Enable Se...

Page 190: ...n be 0 25 0 5 1 2 4 8 second There is RTC overflow counter and it can be adjusted by software 6 12 2 RTC Features There is a time counter second minute hour and calendar counter day month year for use...

Page 191: ...uring manufacture and store the value in Flash memory for retrieval when the product is first power on Time and Calendar counter TLR and CLR are used to load the time and calendar TAR and CAR are used...

Page 192: ...00 sec CAR 00 00 00 TAR 00 00 00 TSSR 1 24 hr mode DWR 6 Saturday RIER 0 RIIR 0 LIR 0 TTR 0 4 FCR Calibration Example 1 Frequency counter measurement 32773 65Hz 32768 Hz Integer part 32773 0x8005 FCR...

Page 193: ...egister 0x0000_0000 CLR RTC_BA 0x010 R W Calendar Loading Register 0x0005_0101 TSSR RTC_BA 0x014 R W Time Scale Selection Register 0x0000_0001 DWR RTC_BA 0x018 R W Day of the Week Register 0x0000_0006...

Page 194: ...28 27 26 25 24 INIR 23 22 21 20 19 18 17 16 INIR 15 14 13 12 11 10 9 8 INIR 7 6 5 4 3 2 1 0 INIR INIR Active Bits Descriptions 0 Active RTC Active Status Read only 0 RTC is at reset state 1 RTC is at...

Page 195: ...rved ENF 15 14 13 12 11 10 9 8 AER 7 6 5 4 3 2 1 0 AER Bits Descriptions 31 17 Reserved Reserved 16 ENF RTC Register Access Enable Flag Read only 1 RTC register read write enable 0 RTC register read w...

Page 196: ...4 3 2 1 0 Reserved FRACTION Bits Descriptions 31 12 Reserved Reserved 11 8 INTEGER Integer Part Integer part of detected value FCR 11 8 Integer part of detected value FCR 11 8 32776 1111 32768 0111 3...

Page 197: ...8 17 16 Reserved 10HR 1HR 15 14 13 12 11 10 9 8 Reserved 10MIN 1MIN 7 6 5 4 3 2 1 0 Reserved 10SEC 1SEC Bits Descriptions 31 22 Reserved Reserved 21 20 10HR 10 Hour Time Digit 19 16 1HR 1 Hour Time Di...

Page 198: ...YEAR 1YEAR 15 14 13 12 11 10 9 8 Reserved 10MON 1MON 7 6 5 4 3 2 1 0 Reserved 10DAY 1DAY Bits Descriptions 31 24 Reserved Reserved 23 20 10YEAR 10 Year Calendar Digit 19 16 1YEAR 1 Year Calendar Digit...

Page 199: ...Reserved Reserved 0 24hr 12hr 24 Hour 12 Hour Mode Selection It indicate that TLR and TAR are in 24 hour mode or 12 hour mode 1 select 24 hour time scale 0 select 12 hour time scale with AM and PM ind...

Page 200: ...RTC_BA 0x018 R W Day of the Week Register 0x0000_0006 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DWR Bits Descriptions 3...

Page 201: ...17 16 Reserved 10HR 1HR 15 14 13 12 11 10 9 8 Reserved 10MIN 1MIN 7 6 5 4 3 2 1 0 Reserved 10SEC 1SEC Bits Descriptions 31 22 Reserved Reserved 21 20 10HR 10 Hour Time Digit 19 16 1HR 1 Hour Time Digi...

Page 202: ...AR 1YEAR 15 14 13 12 11 10 9 8 Reserved 10MON 1MON 7 6 5 4 3 2 1 0 Reserved 10DAY 1DAY Bits Descriptions 31 24 Reserved Reserved 23 20 10YEAR 10 Year Calendar Digit 19 16 1YEAR 1 Year Calendar Digit 1...

Page 203: ...TC Leap year Indication Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved LIR Bits Descriptions 31 1 Reserv...

Page 204: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TIER AIER Bits Descriptions 31 2 Reserved Reserved 1 TIER Time Tick Interrupt...

Page 205: ...31 2 Reserved Reserved 1 TI RTC Time Tick Interrupt Indication 1 It indicates that time tick interrupt has been activated 0 It indicates that time tick interrupt never occurred Software can also clear...

Page 206: ...Tick Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TTR 2 0 Bits Descriptions 31 3 Reserved Reserved 2 0...

Page 207: ...ister can program the frequency of serial clock output This controller contains four 32 bit transmit receive buffers and can provide burst mode operation It supports variable length transfer and the m...

Page 208: ...NUC502 Apr 30 2015 Page 208 of 266 Rev 1 1 6 13 2 SPIMS Timing Diagram The timing diagrams of SPI Master Slave are shown as following SPI Timing Master Alternate Phase SCLK Clock Timing Master...

Page 209: ...iming Slave Alternate Phase SCLK Clock Timing Slave 6 13 3 SPIMS Programming Example When using this SPI controller as a master to access a slave device as slave device with following specifications D...

Page 210: ...ait for interrupt if IE 1 or polling the GO_BUSY bit until it turns to 0 6 Read out the received data from Rx0 7 Go to 3 to continue another data transfer or set SSR 0 or SSR 1 to 0 to inactivate the...

Page 211: ...0_A000 CNTRL SPIMS_BA 0x00 R W Control and Status Register 0x0000_0004 DIVIDER SPIMS_BA 0x04 R W Clock Divider Register 0x0000_0000 SSR SPIMS_BA 0x08 R W Slave Select Register 0x0000_0000 Rx0 SPIMS_BA...

Page 212: ...Interrupt 16 IF Interrupt Flag 0 It indicates that the transfer dose not finish yet 1 It indicates that the transfer is done The interrupt flag is set if it was enable NOTE This bit is read only but...

Page 213: ...Tx_BIT_LEN Transmit Bit Length This field specifies how many bits are transmitted in one transmit receive Up to 32 bits can be transmitted Tx_BIT_LEN 0x01 1 bit Tx_BIT_LEN 0x02 2 bits Tx_BIT_LEN 0x1f...

Page 214: ...1 16 Reserved Reserved 15 0 DIVIDER Clock Divider Register master only The value in this field is the frequency divider of the system clock PCLK to generate the serial clock on the output spi_sclk_o T...

Page 215: ...g 0 sets the line back to inactive state If SSR ASS bit is set writing 1 to any bit location of this field will select appropriate spi_ss_o line to be automatically driven to active state for the dura...

Page 216: ...sters A Write to these registers will actually modify the Data Transmit Registers because those registers share the same FFs Data Transmit Register TX Register Offset R W Description Reset Value Tx0 S...

Page 217: ...00 and CNTRL Tx_NUM is set to 0x3 the core will perform four 32 bit transmit receive successive using the same setting the order is Tx0 31 0 Tx1 31 0 Tx2 31 0 Tx3 31 0 NOTE The RxX and TxX registers s...

Page 218: ...from hanging for an indefinite period of time It is a free running timer with programmable timeout intervals When the specified time interval expires a system reset can be generated If the Watchdog Ti...

Page 219: ...NUC502 Apr 30 2015 Page 219 of 266 Rev 1 1 Watchdog Timer Block Diagram Watchdog Timer Timing Diagram...

Page 220: ...ter 0 0x0000_0005 TCSR1 TMR_BA 04 R W Timer Control and Status Register 1 0x0000_0005 TICR0 TMR_BA 08 R W Timer Initial Control Register 0 0x0000_0000 TICR1 TMR_BA 0C R W Timer Initial Control Registe...

Page 221: ...tions 31 nDBGACK_EN ICE debug mode acknowledge enable 0 When DBGACK is high the TIMER counter will be held 1 No matter DBGACK is high or not the TIMER counter will not be held 30 CEN Counter Enable 0...

Page 222: ...e 11 The timer is operating in the uninterrupted mode The associated interrupt signal is generated when TDR TICR if IE is enabled 26 CRST Counter Reset Set this bit will reset the TIMER counter and al...

Page 223: ...24 23 22 21 20 19 18 17 16 TIC 23 16 15 14 13 12 11 10 9 8 TIC 15 8 7 6 5 4 3 2 1 0 TIC 7 0 Bits Descriptions 31 0 TIC Timer Initial Count This is a 32 bit value representing the initial count Timer...

Page 224: ...imer Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 TDR 31 24 23 22 21 20 19 18 17 16 TDR 23 16 15 14 13 12 11 10 9 8 TDR 15 8 7 6 5 4 3 2 1 0 TDR 7 0 Bits Descriptions 31 0 TDR Timer Data Regist...

Page 225: ...interrupt status of Timer channel 1 0 It indicates that the Timer 1 dose not countdown to zero yet 1 It indicates that the counter of Timer 1 has decremented to zero The interrupt flag is set if it w...

Page 226: ...atchdog timer is Crystal input 0 Using original clock input 1 The clock input will be divided by 256 NOTE When WTTME 1 set this bit has no effect on WDT clock using original clock input 9 nDBGACK_EN I...

Page 227: ...clocks 1 12 sec 10 218 clocks 218 1024 clocks 4 47 sec 3 WTIF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog...

Page 228: ...s the Watchdog timer into a known state It helps reset the Watchdog timer before a timeout situation occurring Failing to set WTR before timeout will initiates an interrupt if WTIE is set If the WTRE...

Page 229: ...and the other have a 16 byte transmitter FIFO TX_FIFO and a 16 byte plus 3 bit of error data per byte receiver FIFO RX_FIFO has been built in to reduce the number of interrupts presented to the CPU Th...

Page 230: ...bits per byte to reduce the number of interrupts presented to the CPU TX shift Register Shifting the transmitting data out serially RX shift Register Shifting the receiving data in serially Modem Con...

Page 231: ...ication register IIR to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt There are four types of interrupts line status interrupt overrun error or...

Page 232: ...ts the stop bit Signal Description THRE Te transmitter holding register is empty Count7 The counter of clock equals to 7 CountF The counter of clock equals to 15 TXDATA_END The data part transfer is f...

Page 233: ...nt F start_detect start_detect start_detect State Definition IDLE The receiver has no data to receive START The receiver receives the start bit RX The receiver receives the desired data PARITY The rec...

Page 234: ...NUC502 Apr 30 2015 Page 234 of 266 Rev 1 1 CountF The counter of clock equals to F RXDATA_END The data received finished PARITY Receiving the parity bit if needed...

Page 235: ...W Transmit Holding Register DLAB 0 Undefined UA_IER UART_BA 0x04 R W Interrupt Enable Register DLAB 0 0x0000_0000 UA_DLL UART_BA 0x00 R W Divisor Latch Register LS DLAB 1 0x0000_0000 UA_DLM UART_BA 0...

Page 236: ...0 R Receive Buffer Register DLAB 0 Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 8 bit Received Data Bits Descriptions 31 8...

Page 237: ...ransmit Holding Register DLAB 0 Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 8 bit Transmitted Data Bits Descriptions 31 8...

Page 238: ...e_o_IE Wake up interrupt enable for Irpt_WakeUp 0 Mask off Irpt_Wakeup 1 Enable Irpt_Wakeup 6 WakeIE Wake up interrupt enable for INTR wakeup 0 Mask off INTR_Wakeup 1 Enable INTR_Wakeup 5 nDBGACK_EN I...

Page 239: ...criptions 0 Mask off INTR_RLS 1 Enable INTR_RLS 1 THREIE Transmit Holding Register Empty Interrupt INTR_THRE Enable 0 Mask off INTR_THRE 1 Enable INTR_THRE 0 RDAIE Receive Data Available Interrupt INT...

Page 240: ...alue UA_DLL UA_BA 0x00 R W Divisor Latch Register LS DLAB 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Baud Rate Divid...

Page 241: ...te Divider High Byte Bits Descriptions 31 8 Reserved Reserved 7 0 Baud Rate Divisor High Byte The high byte of the baud rate divider This 16 bit divider UA_DLM UA_DLL is used to determine the baud rat...

Page 242: ...dentification The IID together with NIP indicates the current interrupt request from UART Interrupt Control Functions UA_IIR 3 0 Priority Interrupt Type Interrupt Source Interrupt Reset control 1 None...

Page 243: ...ndefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 RFITL Reserved TFR RFR FME Bits Descriptions 31 8 Reserved Reserved 7 4 RFITL...

Page 244: ...one This bit must be 1 when other UA_FCR bits are written to otherwise they will not be programmed Line Control Register UA_LCR Register Address R W Description Reset Value UA_LCR UA_BA 0x0C R W Line...

Page 245: ...he data word and parity bits This bit has effect only when bit 3 parity bit enable is set 3 PBE Parity Bit Enable 0 Parity bit is not generated transmit data or checked receive data during transfer 1...

Page 246: ...served Reserved 4 LBME Loop back Mode Enable 0 Disable 1 When the loop back mode is enable the following signals are connected internally SOUT connected to SIN and SOUT pin fixed at logic 1 RTS connec...

Page 247: ...not empty 1 UA_THR is empty THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register TSR The CPU resets this bit when the UA_THR or TX FIFO is loaded This bit also c...

Page 248: ...e contents of the UA_LSR 0 RFDR RX FIFO Data Ready 0 RX FIFO is empty 1 RX FIFO contains at least 1 received data word UA_LSR 4 2 BII FEI PEI are revealed to the CPU when its associated character is a...

Page 249: ...0 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TOIC Bits Descriptions 31 7 Reserved Reserved 6 0 TOIC Time Out Interrupt Co...

Page 250: ...ve the system a warning signal when battery voltage is lower than an absolute reference voltage 6 16 1 Features Maximum conversion rate 400K sample per second Power supply voltage 3 3V Analog input vo...

Page 251: ...V7 V6 V5 V4 V3 V2 V1 Result Flag By control the switch sw1 sw2 sw3 sw4 sw5 sw6 sw7 and sw8 to select the voltage V1 V2 V3 V4 V5 V6 V7 or V8 to be compared to reference voltage which will not be influe...

Page 252: ...ister 0x0000_0000 LV_STS ADC_BA 0x018 R W Low Voltage Detector Status register 0x0000_0000 AUDIO_CON ADC_BA 0x01C R W Audio control register 0x0000_0000 AUDIO_BUF0 ADC_BA 0x020 R W Audio data buffer r...

Page 253: ...enable 21 ADC_INT_EN ADC interrupt enable bit If ADC_INT_EN 0 The ADC interrupt is disable If ADC_INT_EN 1 The ADC interrupt is enable 20 Reserved Reserved 19 LVD_INT Low voltage detector LVD interru...

Page 254: ...V bit If ADC_READ_CONV 0 after the ADC_XDATA is read the ADC no action 11 9 ADC_MUX These bits select ADC input from the 8 analog inputs in normal conversion mode ADC_MUX 000 not available in normal d...

Page 255: ...Descriptions 31 4 Reserved Reserved 3 LV_EN Low voltage detector enable control pin If LV_EN 0 low voltage detector is disable If LV_EN 1 low voltage detector is enable 2 0 SW_CON The low voltage dete...

Page 256: ...18 R W The status register of low voltage detector 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved LV_status Bits...

Page 257: ...it is set an interrupt signal is asserted to the interrupt controller through ADC interrupt source 8 VOL_EN Volume control enable bit If VOL_EN 0 the hardware open the volume control path and open the...

Page 258: ...ompliment format Audio control register AUDIO_BUF2 Bits Descriptions 31 16 AUDIO_DATA1 Converted audio data1 at buffer0 Read Only 16 bit digital audio data in 2 s compliment format 15 0 AUDIO_DATA0 Co...

Page 259: ...dio data7 at buffer3 Read Only 16 bit digital audio data in 2 s compliment format 15 0 AUDIO_DATA6 Converted audio data6 at buffer3 Read Only 16 bit digital audio data in 2 s compliment format 31 30 2...

Page 260: ...0 3 6 V VT Threshold Point 1 30 1 36 1 42 V VT Schmitt trig Low to High threshold point 1 51 1 56 1 60 V VT Schmitt trig High to Low threshold point 1 15 1 21 1 25 V ICC Supply Current FCPU 81MHz 28...

Page 261: ...g Voltage VDD 3 0 3 3 3 6 V Operating Current IDD VDD 3 6V Sample rate 400KHz 600 uA Resolution 10 bit Conversion time 2 5 10 us Sample rate 400 KHz Integral non linear error INL 1 1 LSB Differential...

Page 262: ...NUC502 Apr 30 2015 Page 262 of 266 Rev 1 1 8 Package Specifications LQFP 48 7x7x1 4mm footprint 2 0mm...

Page 263: ...0 024 0 472 0 018 0 50 0 20 0 27 1 45 1 60 10 00 1 40 0 09 0 17 1 35 0 05 0 008 0 011 0 057 0 063 0 393 0 055 0 020 0 004 0 007 0 053 0 002 Symbol Min Nom Max Max Nom Min Dimension in inch Dimension i...

Page 264: ...NUC502 Apr 30 2015 Page 264 of 266 Rev 1 1 LQFP 64 7x7x1 4mm footprint 2 0mm...

Page 265: ...NUC502 Apr 30 2015 Page 265 of 266 Rev 1 1 9 REVISION HISTORY Date Revision Description 2014 02 28 1 0 1 Preliminary version 2015 04 30 1 1 1 Format update...

Page 266: ...to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for vehicular use traf...

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