Nuvoton NAU88L24 Manual Download Page 1

 

Apr 11, 2022 

 Page 1 of 96 

 Rev 2.1 

NAU88L24 

Ultra-Low Power Audio CODEC with Stereo Class D Drivers and Ground-

Referenced Headphone Amplifier with Advanced Headset Detection 

 

GENERAL DESCRIPTION 

The NAU88L24 is an ultra-low power high performance audio codec designed for smartphone, tablet PC, and other 

portable devices that supports both analog and digital audio functions. It includes one I2S/PCM interface, one digital 

mixer, two high quality DACs, two high quality ADCs, two mono differential or one stereo differential analog microphone 

inputs, four analog single-ended microphone inputs, four digital PDM microphone inputs, one single ended stereo 

auxilary or one differential mono inputs, one differential HS mic input, one stereo 2.9W class D loudspeaker amplifier 

driver 

for 4 Ω loading and 5V supply

, and one stereo class G headphone amplifier with automatic headset detection.  

 

The advanced on-chip signal processing engine that includes dynamic range compressors (DRC), 5-band parametric 

equalizer (PEQ), and programmable high pass and notch filter block, can maximize audio quality and eliminate any 

undesirable frequency components. 

 

The NAU88L24 also has powerful headset detection that supports jack insertion / ejection, microphone detection, 

distinct key / short key / long key / key release detection features as well as an integrated frequency locked loop (FLL) 

to support various clocks. 

 
FEATURES

 

 

DAC: 103dB SNR (A-weighted) @ 0dB gain, 1.8V 
and -77dB THD @ 20

mW and RL= 32Ω, DAC 

playback to headphone output mode 

 

ADC: 100dB SNR (A-weighted) @ 0dB MIC gain, 
1.8V, Fs = 48KHz and -85dB THD, 1.8V, MIC gain 
6dB, OSR 128x 

 

1 Digital I2S/PCM I/O port 

 

Dynamic Range Compressor (DRC) 

 

5 Band Parametric Equalizer 

 

1 Headset Microphone, 4 Analog or 4 Digital PDM 
MIC input supports  

 

Stereo .97W Class D Loudsp

eaker @ 4.2V, 8Ω, 

1% THD+N (1.38W @ 5

.0V, 8Ω, 1% THD+N) 

 

 

Class G Headphone Amplifier (27

mW @ 32Ω, 1% 

THD+N)  

 

Stereo Auxiliary Input  

 

Sampling rate from 8K to 96 KHz 

 

Headset Detection  

 

Jack Insertion and Ejection Detection 

 

MIC Detection and Distinct Keys Detection 

 

Package:  
QFN-48 (6X6mm, 0.4mm Pitch) package 
56 Balls WLCSP package with 0.4mm Pitch 
package 

 
 
 

Applications 

 

Tablets / Ultra-Portable Laptops 

 

Smartphones 

 

Audio Docking Systems 

 

Portable Game Players 

 

Cameras 

 

 

Summary of Contents for NAU88L24

Page 1: ...and programmable high pass and notch filter block can maximize audio quality and eliminate any undesirable frequency components The NAU88L24 also has powerful headset detection that supports jack inse...

Page 2: ...or Mixer JKDET DAC QFN 48 Charge Pump MICBIAS MICDET FLL MUX MCLK BCLK FS SCLK SDIO IRQ ADC Effect Volume HPF NF DRC DMIC Interface MUX DMCLK1 2 DMDATA1 2 DAC Effect Volume HPF DRC DACIN ADCOUT BCLK F...

Page 3: ...2 MIC Bias 18 3 2 Digital MIC Inputs 18 3 3 Line Inputs 19 3 4 Programmable Gain Amplifier PGA 19 4 ADC DIGITAL BLOCK 19 4 1 ADC Dynamic Range Compressor DRC 20 4 1 1 Level Estimation 20 4 1 2 Static...

Page 4: ...io Data 39 8 6 PCM Time Slot Audio Data 39 8 7 TDM I2S Audio Data 40 8 8 TDM PCM A Audio Data 40 8 9 TDM PCM B Audio Data 41 8 10 TDM PCM Offset Audio Data 41 9 OUTPUTS 43 9 1 Stereo Class D Speaker O...

Page 5: ...one 54 11 8 Enable DAC to Headphone Low Power MP3 Playback Mode 55 11 9 Enable DAC to Class D Low Power MP3 Playback Mode 55 11 10 Jack Detection 55 12 CONTROL AND STATUS REGISTERS 57 13 TYPICAL APPLI...

Page 6: ...SDIO SCLK FS CPOUTP VDDA VSSA VREF MICDET VDDMIC MICBIAS VDDA VSSA MIC1 DMDATA1 MIC1 DMCLK1 AUX_L MONO VSSCP CPOUTN CPCB CPCA HPL HPR HPCOM TEST VSSSPK VDDSPK VDDSPK SPKOUTL MONO HSMIC MIC2 DMDATA2 MI...

Page 7: ...SPK VSS SPK VDD SPK VSS SPK VDD VSS CP VCC P1 F E D C B A G H 1 2 3 4 5 6 7 TEST 0 4mm 0 4mm 3 66mm 3 22mm VSSA AUXL MONO VDDA VDDA MIC2 DMDATA2 HSMIC MIC2 DMCLK2 MIC1 DMCLK1 VSSA MIC1 DMDATA1 AUX_R...

Page 8: ...nput Headphone ground reference 20 TEST N C Class D amplifier Test point 21 VSSSPK Ground Class D amplifier supply ground 22 VDDSPK Supply Class D amplifier supply 23 VDDSPK Supply Class D amplifier s...

Page 9: ...R DMCLK2 Analog Input Digital Output PGA MIC2 or AUXR Analog Input or Digital Microphone 2 Clock Output 47 MIC2 DMDATA2 Analog Input Digital Input PGA MIC2 Analog Input or Digital Microphone 2 Data In...

Page 10: ...utput for I2S or PCM data C4 IFSEL Digital I O Select Control Interface for 3 wire or 2 wire mode C5 MONO Analog Input PGA Mono C6 MIC1 DMCLK1 Analog Input Digital Output PGA MIC1 Analog Input or Digi...

Page 11: ...round H2 SPKOUTL Analog Output Class D amplifier Left Channel positive Output H3 VDDSPK Supply Class D amplifier supply H4 HPCOM Analog Input Headphone ground reference H5 CPOUTN Analog I O Charge Pum...

Page 12: ...mVPP Input Referred SPK_GAIN 0dB DAC Input DAC_Gain 0dB Ripple Applied to VDDSPK 4 2V 80 dB Efficiency VDDSPK 4 2V at 1 THD RL 8 86 XTALK Channel Crosstalk Left Channel to Right Channel PO 500mW f 1kH...

Page 13: ...ut 98 Reference VOUT 0dBFS A Weighted Stereo Input Gain 0dB fs 48kHz 100 dB PSRR Power Supply Rejection Ratio VRIPPLE 200mVPP applied to VDDA fRIPPLE 217Hz Input Referred MIC_GAIN 0dB Differential Inp...

Page 14: ...on VDDMIC VDDA 1 2V VDDB VDDC 0 6V Absolute Maximum Ratings Parameter Min Max Units Digital Supply Range 0 3 2 2 V Digital I O Supply Range 0 3 6 0 V Analog Supply Range 0 3 2 2 V Headphone Supply Ran...

Page 15: ...delta converters which are suitable for a very wide range of applications The ADCs and DACs have functions that individually support analog mixing and routing The ADC and DAC blocks also support adva...

Page 16: ...and flexibility There is a left and right input path with four input pins each which can be used to capture signals from single ended and differential sources Each channel has a fully differential pro...

Page 17: ...the application has large decoupling capacitors on the inputs there is an option to pre charge the capacitors to minimized pops and clicks during startup Please see register FEPGA_II ADC_CTRL REG0X78...

Page 18: ...e MIC bias pin which can be used to power electret and digital microphones This pin can be enabled by using MIC_BIAS POWERUP REG0X74 8 and the level can be set by using MIC_BIAS MICBIASLVL1 REG0X74 2...

Page 19: ...ROL PUPR REG0X7F 13 and POWER_UP_CONTROL PUPL REG0X7F 12 and are controlled using FEPGA FEPGA_MODER REG0X77 7 4 and FEPGA FEPGA_MODEL REG0X77 3 0 Application Notes The PGA can accept either differenti...

Page 20: ...able 2 ADC Channel Input Definitions 4 1 ADC Dynamic Range Compressor DRC The NAU88L24 includes DRCs for the four channels in the ADC However to control the DRC the four channels have been paired and...

Page 21: ...DRC_CMP2_SLP _ADC_CH01 REG0X3A 8 6 DRC_KNEE_IP12_ADC_CH01 DRC_KNEE2 _IP_ADC_CH01 REG0X38 13 8 2 3 DRC_SLOPE_ADC_CH23 DRC_CMP2_SLP _ADC_CH23 REG0X3E 8 6 DRC_KNEE_IP12_ADC_CH23 DRC_KNEE2 _IP_ADC_CH23_R...

Page 22: ...st the effective audio volume coming from each ADC using a two stage volume control This allows the gain to be adjusted from 128dB to 50dB Also included is a mute value that will reduce the ADC output...

Page 23: ...d NOTCH_FILTER_2 NFA1 REG0X28 13 0 according the table below Application Notes The filter operation and settings are the same for both ADCs NOTCH_FILTER_2 NOTCH_DLY_DIS REG0X28 14 is an optional delay...

Page 24: ..._DGAIN_C TRL REG0X2F ADC_CH2_S EL DGAIN_ADC_C H2 DACTOADC_CH2_S EL DACTOADC_ATTU_C H2 3 ADC_CH3_DGAIN_C TRL REG0X30 ADC_CH3_S EL DGAIN_ADC_C H3 DACTOADC_CH3_S EL DACTOADC_ATTU_C H3 Table 8 ADC Digital...

Page 25: ...companding standards on both transmit and receive sides A law and law The A law algorithm is primarily used in European communication systems and the law algorithm is primarily used by North America...

Page 26: ...udio processing that may be required as the data is passed from other stages of the system DAC input source from ADC by setting PORT0_I2S_PCM_CTRL_1 ADDAP REG0X1C 7 1 5 1 DAC Dynamic Range Control DRC...

Page 27: ...0 31 Ts 1023 Ts 0101 63 Ts 2047 Ts 0110 127 Ts 4095 Ts 0111 255 Ts 8191 Ts 1000 511 Ts 16383 Ts 1001 1023 Ts 32757 Ts 1010 2047 Ts 65535 Ts 1011 4095 Ts 1100 8191 Ts Table 15 DAC Static Curve Attack a...

Page 28: ...EQ2C REG0X2A 6 5 EQ2_EQ3 EQ2BW REG0X2A 7 EQ2_EQ3 EQ2G REG0X2A 4 0 3 650Hz 1 4kHz EQ2_EQ3 EQ3C REG0X2A 14 13 EQ2_EQ3 EQ3BW REG0X2A 15 EQ2_EQ3 EQ3G REG0X2A 12 8 4 1 8kHz 4 1kHz EQ4_EQ5 EQ4C REG0X2B 6 5...

Page 29: ...REG0X33 and ADC_TO_DAC_ST REG0X34 for DAC channels 0 and 1 CH DAC Output Mixer Select ADC Channel Select ADC Channel Gain I2S Channel Select I2S Channel Gain 0 MIXLR_SEL_CH0 REG0X32 15 ADCTODAC_CH0_ S...

Page 30: ...K_GATING_ENA CLK_EQ_EN REG0X02 2 enables clock gating for the equalizer CLK_DIVIDER CLK_DAC_SRC REG0X03 5 4 can scale the clock speed TDM_CTRL DAC_LSEL REG0X20 7 6 selects DAC channel 0 slot number in...

Page 31: ...MCLK Register CLK_DIVIDER 0 1 0 1 MCLK_SRC CLK_CODEC_SRC CLK_ADC_SRC CLK_ADC_PL CLK_ADC Register CLK_GATING_EN Figure 8 MCLK and ADC_CLK Frequency Selection Bits MCLK_SRC 0000 Divide by 1 0001 Invert...

Page 32: ...he MCLK frequency The ADC clock frequency is set by CLK_DIVIDER CLK_CODEC_SRC REG0X03 13 and CLK_DIVIDER CLK_ADC_SRC REG0X03 7 6 registers and must remain smaller than 6 144MHz For example this device...

Page 33: ...0X07 11 10 or to run the FLL as a free running clock enable FLL6 DCO_EN REG0X09 15 set FLL_DCO_RSV DOUT2DCO_RSV REG0X0A 15 0 to 16 hF13C and BOOST BIASEN REG0X76 12 1 The FLL output frequency is deter...

Page 34: ...less than or equal to 13 5MHz FLL3 GAIN_ERR REG0X06 14 12 and FLL5 FLL_CLK_REF_DIV_4CHK REG0X07 14 12 are used to control the gain and resolution respectively It is recommended that the default settin...

Page 35: ...ce releases the SDIO bus after transmitting eight bits and during the ninth clock cycle the receiver slave pulls the SDIO line LOW to acknowledge the reception of the eight bits of data To terminate a...

Page 36: ...ut with R W 1 After the NAU88L24 recognizes its Device Address the second time it will transmit an ACK followed by a two byte value containing the 16 bits of data in the NAU88L24 control registers req...

Page 37: ...ng to any other valid register address terminates the reset condition but all registers will now be set to their power on default values 8 Digital Audio Interfaces The NAU88L24 can be configured as ei...

Page 38: ...n the image below FS SDI SDO BCLK N 1 N 2 1 0 N 1 N 2 1 0 CHANNEL 0 CHANNEL 1 MSB LSB MSB LSB Figure 18 Right Justified Audio Interface 8 2 Left Justified Audio Data In left justified mode the MSB is...

Page 39: ...the FS pulse rising edge and channel 1 MSB is clocked on the next BCLK after channel 0 LSB This can be seen in the figure below FS SDI SDO BCLK N 1 1 0 N 1 1 0 MSB LSB LSB MSB N 2 N 2 CHANNEL 0 CHANN...

Page 40: ...RT0_I2S_PCM_CTRL_2 ADCDAT_OE REG0X1D 4 by default actively drives the SDO pin never in high impedance state This needs to be disabled in order to share the data line 8 7 TDM I2S Audio Data In I2S mode...

Page 41: ...ch the ADC data is clocked This increases the flexibility of the NAU88L24 to be used in a wide range of system designs One key application of this feature is to enable multiple NAU88L24 or other devic...

Page 42: ...HANNEL 1 CHANNEL 3 Figure 27 TDM PCM Offset Audio Format Application Notes When using PORT0_LEFT_TIME_SLOT TSLOT_L REG0X1E 9 0 for time slot shift in TDM mode the four channels will shift together for...

Page 43: ...N_1 CLASSDGAIN1L REG0X6D 4 0 and CLASSD_GAIN_1 CLASSDGAIN1R REG0X6D 12 8 for driver 1 and CLASSD_GAIN_2 CLASSDGAIN2L REG0X6E 4 0 and CLASSD_GAIN_2 CLASSDGAIN2R REG0X6E 12 8 for driver 2 Parameter Symb...

Page 44: ...ll be disabled for 47ms The output drivers will then be re enabled and checked for a short circuit again If the short circuit is still present for another 14 s the cycle will repeat until the short ci...

Page 45: ...eaker Outputs Connected to Speaker with Ferrite Bead Filters These ferrite bead filters offer high impedance at high frequencies so that it will function as a low pass filter around the desired audio...

Page 46: ...w is default which gives the low voltage output This is used for when the headphones have attenuated signals CLASSG CLASSG_THRSLD REG0X50 5 4 sets the threshold from 1 16 to 1 4 Full Scale CHARGE_PUMP...

Page 47: ...at the microphone pin It also supports Long and Short button press detection and each key can activate an interrupt on the IRQ pin Each sequence associated with these detection mechanisms can be execu...

Page 48: ...tion is valid and SAR_ADC_DATA_OUT SARADC_DOUT has a value between 0xFF and 0x00 If the jack doesn t have microphone the value is equal to 0x00 10 3Key Button Detection This feature allows software pr...

Page 49: ...ophone bias voltage is tied to the MICBIAS pin then the SAR ADC digital output signal decimal representation can be described as 255 Amb is the MIC bias factor given by MIC_BIAS MICBIASLVL1 REG0X74 2...

Page 50: ...no button is pressed the SARADC_DOUT decimal output is SARADC_DOUT 255 x 1 53 x 1 8 x 1 1 53 x 1 8 x 10k 2k 10k 212 2 When a button with 4k Ohm series resistance is pressed the SARADC_DOUT output bec...

Page 51: ...ve been pressed Once the SAR ADC has been enabled using SAR_ADC SAR_ENA REG0X13 12 the SAR ADC enters a sampling phase During this phase the voltage level on the MIC input is sampled at a speed determ...

Page 52: ...e external headset jack interrupt and clears the x11 register to reset for further interrupts The headphone and microphone are disabled accordingly and it resumes waiting for further interrupts Jack E...

Page 53: ...CDC_CTRL REG0X78 15 10 to the inputs used 5 Set BOOST DISCHRG REG0X76 11 1 6 Wait 1ms 7 Set BOOST DISCHRG REG0X76 11 0 8 Set FEPGA_II ACDC_CTRL REG0X78 15 10 0 9 Set FEPGA_ATTENUATION FEPGA_ATTNL REG0...

Page 54: ...Set CHARGE_PUMP_AND_POWER_DOWN_CONTROL PD_DAC REG0X80 9 8 11 5 Disable the I2S to DAC3 and DAC4 paths 11 6Enable Disable Class D Driver It is assumed that VREF BOOST BIASEN REG0X76 12 System Master Cl...

Page 55: ...0 00 and CHARGE_PUMP_AND_POWER_DOWN_CONTROL PULL_SPKR_DWN REG0X80 13 12 11 on next I2C command 4 SET POWER_UP_CONTROL PUP_DRV_INSTG REG0X7F 3 2 00 on next I2C command The disable sequence is only nece...

Page 56: ...y MIC_BIAS MICBIASLVL1 2 0 REG0X74 2 0 0 then turn on mic bias MIC_BIAS POWERUP REG74 8 1 4 Set jack ejection de bounce time 10ms by JACK_DET_CTRL EJECT_DT 1 0 REG0XD 3 2 2 5 Optimize SARADC by follow...

Page 57: ...0_I2S_PCM_CTRL_1 57 TEST_MODE 1D PORT0_I2S_PCM_CTRL_2 58 I2C_DEVICE_ID 1E PORT0_LEFT_TIME_SLOT 59 SAR_ADC_DATA_OUT 1F PORT0_RIGHT_TIME_SLOT 66 BIAS_ADJ 20 TDM_CTRL 67 PGA_GAIN 23 ADC_HPF_FILTER 68 TRI...

Page 58: ...l 0 Disable DEFAULT 1 Enable ADC_CH0_D MIC_MODE ADC Path CH0 DMIC Mode Enable Control 0 Disable DEFAULT 1 Enable DAC_CH1_EN DAC Path CH1 Enable Control 0 Disable DEFAULT 1 Enable DAC_CH0_EN DAC Path C...

Page 59: ...able DEFAULT 1 Enable DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 3 CLK_DIVI DER SYSCLK_SRC Master Clock Source Select 0 MCLK_PIN DEFAULT 1 DCO_CLK CLK_CODEC_ SRC ADC DAC Clock Source Select 0 From...

Page 60: ...0001000 For input clock frequency 64KHz 0010000 For input clock frequency 32KHz 0100000 For input clock frequency 8KHz 1000000 For input clock frequency 4KHz DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x...

Page 61: ...t the time that FLL must stay within the lock in range before lock signal goes high DEFAULT 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xC000 9 FLL6 DCO_EN FLL Free running Mode Enable Control Need to enable 0x7...

Page 62: ...set to 1 generates an interrupt when the right side Class D driver is shutting down due to an over current or high temperature condition Bit2 RESERVED Bit3 RESERVED Bit4 When set to 1 generates an in...

Page 63: ...Key Interrupt Disable Control 0 Enable DEFAULT 1 Disable SHRT_SHTD WN_INT_DIS APR Emergency Short Circuit Shutdown Interrupt Disable Control 0 Enable interrupt interrupt status read from register or I...

Page 64: ...DEFAULT 010 170k Ohms 011 360k Ohms 1XX Short COMP_SPEE D Compare Cycle Time Select The total conversion has 8 compare cycles 00 500ns 01 1us DEFAULT 10 2us 11 4us SAMPLE_SPE ED Sampling Phase Time S...

Page 65: ...C_VD ET_THR5 Key 5 SAR ADC Threshold Level Control Binary values from 0 to 255 DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 1 8 VDET_TH RESHOL D_4 SARADC_VD ET_THR6 Key 6 SAR ADC Threshold Level Con...

Page 66: ...fied 10 Standard I2S format 11 PCMA or PCMB audio data format option DEFAULT DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0x000B 1 D PORT0_I2 S_PCM_C TRL_2 I2S_TRI I2S Tri State Enable Control 0 Normal mod...

Page 67: ...00 252 x MCLK DEFAULT 01 253 x MCLK 10 254 x MCLK 11 255 x MCLK DIS_FS_SHO RT_DET Short Gram Sync Detection Logic Enable Control 0 Enable DEFAULT 1 Disable TSLOT_R Right Channel PCM Time Slot Start V...

Page 68: ...0 0 0 0 0 0 0 0 0 0x0000 2 4 ADC_FILT ER_CTRL ADC_ZC_EN ADC Gain Zero Crossing Update Enable Control 0 Disable DEFAULT 1 Enable RESERVED RESERVED SMPL_RATE Audio Data Sample Rate Indication 000 48KHz...

Page 69: ...1110 14 1111 15 DAC_STEP_S EL DAC Output Step Select 0XX Use internal step DEFAULT 100 Clock DAC 101 Delay 1 cycle of MCLK 110 Delay 2 cycles of MCLK 111 Delay 3 cycles of MCLK DACPL DAC Output Polari...

Page 70: ...RESERVED EQON EQ Enable Control 0 Disable DEFAULT 1 Enable EQMODE EQ Block Assignment Mode Select 0 EQ block assigned on ADC 1 EQ block assigned on DAC DEFAULT EQ1BW EQ1 Bandwidth Control 0 Narrow ban...

Page 71: ...0x00 12dB 0x01 11dB 0x0C 0dB DEFAULT 0x17 11dB 0x18 12dB EQ4BW EQ4 Bandwidth Control 0 Narrow bandwidth DEFAULT 1 Wide bandwidth EQ4C EQ4 Band pass Center Frequency Select 00 1 8KHz 01 2 4KHz DEFAULT...

Page 72: ...r Source Select 00 ADC CH0 DEFAULT 01 ADC CH1 10 ADC CH2 11 ADC CH3 DGAIN_ADC_ CH1 ADC CH1 Digital Gain Control Step size is 0 5dB 0x000 128dB 0x001 127 5dB 0x100 0dB DEFAULT 0x163 49 5dB 0x164 50dB D...

Page 73: ...AMUTE_CTRL Auto Mute Control 0 Both DAC channels must have 0 values for 1024 samples before AMUTE turns on DEFAULT 1 Either Ch0 or Ch1 must have 1024 consecutive zero samples SMUTE_EN Soft Mute Enable...

Page 74: ...t channel DGAIN_CH1_ DAC DAC CH1 Digital Gain Control Step size is 0 5dB 0x000 128dB 0x001 127 5dB 0x100 0dB DEFAULT 0x163 49 5dB 0x164 50dB DEFAULT 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0x0100 3 4 ADC_TO_...

Page 75: ...PE_ADC_ CH01 DRC_NG_SLP _ADC01 DRC ADC CH01 Noise Gate Slope 00 1 1 01 2 1 10 4 1 DEFAULT 11 8 1 DRC_EXP_SL P_ADC01 DRC ADC CH01 Expansion Slope 00 1 1 01 2 1 10 4 1 DEFAULT 11 RESERVED DRC_CMP2_S LP...

Page 76: ...0011 511 Ts 0100 1023 Ts 0101 2047 Ts 0110 4095 Ts 0111 8191 Ts DEFAULT 1000 16383 Ts 1001 32757 Ts 1010 65535 Ts DEFAULT 0 0 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0x3457 3 C DRC_KNE E_IP12_A DC_CH23 DRC_ENA_A...

Page 77: ...e Higher Region 000 0 001 1 2 010 1 4 011 1 8 100 1 16 101 110 RESERVED 111 1 DEFAULT DRC_LMT_SL P_ADC_CH23 DRC ADC CH23 Limiter Slope 000 0 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 DE...

Page 78: ...AULT X X X X X X X X X X X X X X X X READ ONLY 4 3 DRC_GAI NL_ADC3 DRC_GAIN_A DC3 DRC Gain Read Out For ADC CH3 15 10 for integer 9 0 for fraction DEFAULT X X X X X X X X X X X X X X X X READ ONLY 4 5...

Page 79: ...127 Ts 0111 255 Ts 1XXX RESERVED DRC_PK_CO EF2_DAC DRC DAC Peak Detection Release Time Ts 1 SMPL_RATE 0000 63 Ts 0001 127 Ts 0010 255 Ts 0011 511 Ts 0100 1023 Ts DEFAULT 0101 2047 Ts 0110 4095 Ts 011...

Page 80: ...th Enable Control Each Bit enables according DAC path If CLASSG_EN 1 and CLASSG_CMP_EN 00 supplies stay at 9 0 Disable DEFAULT 1 Enable Bit 0 Left DAC Bit 1 Right DAC CLASSG_EN Class G Function Enable...

Page 81: ...EFAULT 1 Enable SARADC_DO UT SAR ADC Read Out DEFAULT X X X X X X X X X X X X X X X X Read Only 6 6 BIAS_AD J RESERVED RESERVED VMIDEN VMID Enable Control 0 Disable DEFAULT 1 Enable VMIDSEL VMID Tie o...

Page 82: ...ve current DEFAULT 1 High drive current DMIC_SLEW DMIC Clock Slew Rate Select For high Cload 20pF use faster slew rate 000 Slowest slew rate DEFAULT 111 Fastest slew rate DEFAULT 0 0 0 0 0 0 0 0 0 0 0...

Page 83: ...0 0 0 0 0 0 0 0 0 0x0000 6 C GAIN_LO CLK_DAC_IN V DAC Clock Polarity 0 Non inverted DEFAULT 1 Inverted RESERVED RESERVED POLARITY Mixer Output Polarity 0 Non inverted DEFAULT 1 Inverted Bit0 Inverts...

Page 84: ...00002 1dB 11000 23dB 11001 24dB DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 7 1 ANALOG _ADC_1 RESERVED RESERVED DEFAULT 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0x0011 7 2 ANALOG _ADC_2 RESERVED RESERVED AD...

Page 85: ...0 0 0 0 0 0 1 0 0 0 0x0008 7 4 MIC_BIAS INT2KB MICBIAS1 Internal 2K Ohm Resistor For MCGND Enable Control 0 Disable DEFAULT 1 Enable INT2KA MICBIAS1 Internal 2K Ohm Resistor For MCGND Enable Control 0...

Page 86: ...hort circuit Shutdown Enable Control 0 Driver shuts down after 16 3 sec debounce when shortage detected IRQ pin Interrupt is generated When SHRT_ SHTDWN_ DIG_EN 0 APR_EMRGNCY_SHTDWN is cleared if the...

Page 87: ...nable Control Effective when DISCHRG 1 0 Disable DEFAULT 1 Enable Bit 0 AUXL MONO MONO HSMIC QFN AUXL MONO MONO WLCSP Bit 1 MONO HSMIC HSMIC QFN AUX_R HSMIC HSMIC WLCSP Bit 2 MIC1 DMCLK1 MIC2 DMCLK2 B...

Page 88: ...Step size is 1dB 0x00 0dB DEFAULT 0x01 1dB 0x1E 30dB 0x1D 29dB ATT0HSL LDAC To Light Headset Attenuation Control Step size is 1dB 0x00 0dB DEFAULT 0x01 1dB 0x1E 30dB 0x1D 29dB DEFAULT 0 0 0 0 0 0 0 0...

Page 89: ...p Enable Control 0 Disable DEFAULT 1 Enable PRECHARGE VPOS Pre charge Enable Control For faster startup 0 Disable DEFAULT 1 Enable DISCHARGEV EE VEE Pad Discharge Enable Control 0 Disable DEFAULT 1 En...

Page 90: ...DMDATA1 VDDSPK GPIO2 JKDET VSSSPK VDDSPK VSSA VDDA FS SPKOUTL CPOUTP MONO HSMIC 5V 5V 5V 5V 1 8V 1 8V 3 3V 1 2V 3 3V 200 Ohm To From Processor 4k7 1 2 3 4 sw1 sw2 SPK_L SPK_R GND MIC Line In 4u7 2u2 2...

Page 91: ...67 L F THICKNESS A3 0 203 REF LEAD WIDTH b 0 20 0 25 0 30 BODY SIZE D 7 0 BSC E 7 0 BSC LEAD PITCH e 0 5 BSC LEAD LENGTH L 0 30 0 40 0 50 PACKAGE EDGE TOLERANCE aaa 0 10 MOLD FLATNESS bbb 0 10 COPLAN...

Page 92: ...Apr 11 2022 Page 92 of 96 Rev 2 1 14 2 QFN48L 6x6MM 2 QFN 48L 6X6 MM 2 Thickness 0 9 mm Max Pitch 0 4mm...

Page 93: ...PL MIC BIAS MIC DET VDD MIC CP OUTN CP OUTP CPCB BCLK IFSEL HP COM CPCA GP2 JKDET GP4 SDO SCLK GP1 CSB SPK VDD SPK VSS SPK VDD SPK VSS SPK VDD VSS CP VCC P1 F E D C B A G H 1 2 3 4 5 6 7 TEST 0 4mm 0...

Page 94: ...Dimension Package Package Material NAU88L24YG 7 x 7 mm QFN 48 Green NAU88L24IG 6 X 6 mm QFN 48 Green NAU88L24VG 3 22 X 3 66 mm 56 Balls WLCSP Green Package Type Y 48 Pin QFN Package I 48 Pin QFN Packa...

Page 95: ...y expressed Removal of YG package 1 4 Ma 2018 P 24 ADC DRC EXP SLOPE register bit map correction P 22 P28 P29 P33 Add Reg0x1C 7 ADDAP in ADC DAC and DAC mixer note Application diagram add low pass fil...

Page 96: ...uipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for vehicular use traffic s...

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