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ISD91200 Series Technical Reference Manual

Release Date: Sep 16, 2019

- 362 -

Revision 2.4

6.8

In-System Programming (ISP)

The program and data flash memory support both in hardware In-Circuit Programming (ICP) and
firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-Wire
Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang-writers are available
to reduce programming and manufacturing costs. For firmware updates in the field, the I91200 provides
an ISP mode allowing a device to be reprogrammed under software control.

ISP is performed without removing the device from the system. Various interfaces enable LDROM
firmware to fetch new program code from an external source. A common method to perform ISP would
be via a UART controlled by firmware in LDROM. In this scenario, a PC could transfer new APROM
code through a serial port. The LDROM firmware receives it and re-programs APROM through ISP
commands. An alternative might be to fetch new firmware from an attached SD-Card via the SPI
interface.

6.8.1

ISP Procedure

The I91200 will boot from APROM or LDROM from a power-on reset as defined by user configuration
bit CBS. If user desires to update application program in APROM, the FMC_ISPCTL.BS can be set
to ’1’ and a software reset issued. This will cause the chip to boot from LDROM. An example flow
diagram of the ISP sequence is shown in Figure 6-5.

The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence

to gain

access. This procedure is to protect the flash memory from

unintentional access.

To enable ISP functionality software must first ensure the ISP clock (CLK_AHBCLK.ISPCKEN) is
present then set the FMC_ISPCTL.ISPEN bit.

Several error conditions are checked after software writes the ISPTRIG register. If an error condition
occurs, ISP operation is not started and the ISP fail flag (FMC_ISPCTL.ISPFF) will be set instead. The
ISPFF flag will remain set until it is cleared by software. Subsequent ISP procedure can be started even
if ISPFF is set. It is recommended that software check ISPFF bit and clear it after each ISP operation if
set.

When ISPTRIG register is set, the CoretxM0 CPU will wait for ISP operation to finish, during this period;
peripherals operate as usual. If any interrupt requests occur, CPU will not service them until ISP
operation finishes. As the ISP functions affect the operation of the flash memory M0 instruction pipeline
should be flushed with an ISB (Instruction Synchronization Barrier) instruction after the ISP is triggered.

CPU writes ISPTRIG

ISP operation

HCLK

HREADY

CPU is halted but other peripherials keep working

ss

ss

Figure 6-4 ISP Operation Timing

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Summary of Contents for ISD91200 Series

Page 1: ...rty of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of ISD ARM Cortex M0 microcontroller ba...

Page 2: ...Management Unit PMU 111 5 3 1 Clock Generator 111 5 3 2 System Clock SysTick Clock 112 5 3 3 Peripheral Clocks 113 5 3 4 Power Management 113 5 3 5 Register Map 115 5 3 6 Register Description 116 5 4...

Page 3: ...terface SPI0 Controller 218 5 9 1 Overview 218 5 9 2 Features 218 5 9 3 SPI0 Block Diagram 218 5 9 4 SPI0 Function Descriptions 219 5 9 5 SPI Timing Diagram 229 5 9 6 SPI Configuration Examples 232 5...

Page 4: ...ap 332 5 15 6 Register Description 333 5 16 Volume Control 352 5 16 1 Overview and feature 352 5 16 2 Volume Control Register Map 352 5 16 3 Volume Control register Description 353 6 FLASH MEMORY CONT...

Page 5: ...or Frequency Measurement and Control 413 7 5 Automatic Level Control ALC 419 7 5 1 Overview and Features 419 7 5 2 Register Map 423 7 5 3 Register Description 424 7 6 Capacitive Sensing Scan CSCAN and...

Page 6: ...ISD91200 Series Technical Reference Manual Release Date Sep 16 2019 6 Revision 2 4 10 ORDERING INFORMATION 471 11 REVISION HISTORY 472 IMPORTANT NOTICE 473...

Page 7: ...15 Acknowledge on the I2C bus 154 Figure 5 16 Legend for the following four figures 155 Figure 5 17 Master Transmitter Mode 156 Figure 5 18 Master Receiver Mode 157 Figure 5 19 Slave Transmitter Mode...

Page 8: ...K 231 Figure 5 52 SPI1 Block Diagram 250 Figure 5 53 SPI1 Master Mode Application Block Diagram 251 Figure 5 54 SPI1 Slave Mode Application Block Diagram 252 Figure 5 55 Two Transactions in One Transf...

Page 9: ...0 Figure 4 Block diagram of instrumentation amplifier IA 391 Figure 7 5 DPWM Block Diagram 398 Figure 7 6 VMID Reference Generation 409 Figure 7 7 LDO Power Domain 410 Figure 7 8 Oscillator Frequency...

Page 10: ...ISD91200 Series Technical Reference Manual Release Date Sep 16 2019 10 Revision 2 4 Figure 7 26 A D Controller Interrupt 456 Figure 7 27 Conversion Result Mapping Diagram of Single end Input 459...

Page 11: ...aving modes including a Deep Power Down DPD mode drawing less than 1 A A micro power 10KHz oscillator can periodically wake up the device from deep power down to check for other events A Standby Power...

Page 12: ...ROM Memory 64K 128K bytes Flash EPROM for program code and data storage Mini cache to maintain near zero wait state memory access Support In system program ISP and In circuit program ICP application c...

Page 13: ...ectable time out period from micro seconds to seconds depending on clock source WDT can wake up power down sleep Interrupt or reset selectable on watchdog time out RTC Real Time Clock counter second m...

Page 14: ...ate as either master or slave Capable of handling 8 16 24 and 32 bit word sizes Mono and stereo audio data supported I2 S and MSB justified data format supported Two 8 word FIFO data buffers are provi...

Page 15: ...l Reference Manual Release Date Sep 16 2019 15 Revision 2 4 Digital Microphone interface Standby current in STOP mode with SRAM retention 10 A at 25 C Operating Temperature 40C 85C Package All Green p...

Page 16: ...GPIOA 10 GPIOB 15 GPIOB 14 MICN MICP VSS GPIOB 4 GPIOA 4 MICBIAS 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 17 18 19 20 21 22 23 24 25 26 27 28 64 63 62 61 60 59 58 57 56 55 54 53...

Page 17: ...Port A bit 1 SPI0_MOSI0 O 1 1st Master Out Slave In for SPI0 interface I2S0_BCLK I O 3 Bit Clock for I2S interface 9 PA 2 I O 0 General purpose input output pin Port A bit 2 SPI0_SCLK0 I O 1 Serial Cl...

Page 18: ...General purpose input output pin Port A bit 8 I2C0_SDA I O 1 Serial Data I2C interface UART1_TX O 2 Transmit channel of UART 1 UART0_RTS O 3 UART 0 Request to Send Output 27 PA 9 I O 0 General purpos...

Page 19: ...r 1 DPWM_N O 3 Audio PWM negative 39 VREG P Logic regulator output decoupling pin A 1 F capacitor returning to VSSD must be placed on this pin 40 NC 41 VCCD P Main Digital Supply for Chip Supplies all...

Page 20: ...ose input output pin analog capable Port B bit 7 I2S0_SDO O 1 Serial Data Output for I2S interface CS7 AI Touch scan channel 7 C1N AI Comparator 1 negtive input SAR9 AI SARADC channel 9 50 PB 8 I O 0...

Page 21: ...I 3 SARADC Trigger CS13 AI Touch scan channel 13 SAR5 AI SARADC channel 5 56 PB 14 I O 0 General purpose input output pin analog capable Port B bit 14 SPI0_SCLK0 I O 1 1st Serial Clock for SPI0 inter...

Page 22: ...KB Embedded Flash 128KB AHB to APB bridge Flash Mem Controller I2C PWM Speaker Driver SPI0 1 Timers PWM Debug interface GPIO CLK CTRL 50MHz Internal Osc 32kHz RTC Osc SDADC UART0 1 SARADC I2S LDO 3 0V...

Page 23: ...essor that features The ARMv6 M Thumb instruction set Thumb 2 technology ARMv6 M compliant 24 bit SysTick timer A 32 bit hardware multiplier The system interface supports little endian data accesses T...

Page 24: ...am Counter Sampling Register PCSR for non intrusive code profiling Single step and vector catch capabilities Bus interfaces Single 32 bit AMBA 3 AHB Lite system interface that provides simple integrat...

Page 25: ...eral interrupt source identify 5 2 2 System Reset The system reset includes one of the list below event occurs For these reset event flags can be read by SYS_RSTSTS register The Power On Reset The low...

Page 26: ...RAM and RTC during standby mode for low power operation The outputs of internal voltage regulators VREG and VDDB require external decoupling capacitors which should be located close to the correspondi...

Page 27: ...ers 5 15 5 0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers 6 9 APB1 Modules Space 0x4000_0000 0x400F_FFFF 0x4000_4000 0x4000_7FFF WDT_BA Watch Dog Timer Control Registers 5 12 1 0x4000_8...

Page 28: ...6 0x400E_0000 0x400E_FFFF SDADC_BA Analog Digital Converter ADC Registers 7 1 5 0x400F_0000 0x400F_7FFF SBRAM_BA Standby RAM Block Address space System Control Space 0xE000_E000 0xE000_EFFF 0xE000_E01...

Page 29: ...ctions control register 0x0000_0000 SYS_WKCTL SYS_BA 0x54 R W WAKEUP pin control register 0x0000_0006 SYS_REGLCTL SYS_BA 0x100 R W Register Lock Control 0x0000_0000 SYS_IRCTCTL SYS_BA 0x110 R W Oscill...

Page 30: ...y this chip Register Offset R W Description Reset Value SYS_PDID SYS_BA 0x00 R Product ID 0xXXXX_XXXX 31 30 29 28 27 26 25 24 PDID 31 24 23 22 21 20 19 18 17 16 PDID 23 16 15 14 13 12 11 10 9 8 PDID 1...

Page 31: ...wer on Reset Flag The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down 0 No detected 1 A power on Reset has occurred This bit is cleared by w...

Page 32: ...ol Register in system control registers of Cortex_M0 kernel This bit is cleared by writing 1 to itself 4 Reserved Reserved 3 LVRF Low Voltage Reset Flag The LVRF flag is set if pervious reset source o...

Page 33: ...t this bit to 0 to release from the reset state 0 Normal operation 1 PDMA IP reset 1 CPURST CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller FMC this bi...

Page 34: ...ed BIQRST UART1RST UART0RST 15 14 13 12 11 10 9 8 Reserved Reserved DPWMRST SPI0RST SPI1RST Reserved Reserved I2C0RST 7 6 5 4 3 2 1 0 TMR1RST TMR0RST Reserved Reserved Reserved Reserved Reserved Reser...

Page 35: ...15 14 Reserved 13 DPWMRST DPWM Speaker Driver Reset 0 Normal Operation 1 Reset 12 SPI0 RST SPI0 Controller Reset 0 Normal Operation 1 Reset 11 SPI1 RST SPI1 Controller Reset 0 Normal Operation 1 Reset...

Page 36: ...trols Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr Each bit controls a group of four GPIO pins 1 GPIOB 15 14 13 12 input Schmitt...

Page 37: ...22 SSGPAG3 this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr Each bit controls a group of four GPIO pins 1 GPI...

Page 38: ...utput Dr Each bit controls a group of four GPIO pins 1 GPIOA 3 2 1 0 Output high slew rate 0 GPIOA 3 2 1 0 Output low slew rate 16 SSGPAG0 this Register Controls Whether the GPIO Input Buffer Schmitt...

Page 39: ...FP SYS_BA 0x38 R W GPIOA multiple alternate functions control register 0x0000_0000 31 30 29 28 27 26 25 24 PA15MFP PA14MFP PA13MFP PA12MFP 23 22 21 20 19 18 17 16 PA11MFP PA10MFP PA9MFP PA8MFP 15 14 1...

Page 40: ...FP Alternate Function Setting for PA8MFP 00 GPIO 01 I2C0_SDA 10 UART1_TX 11 UART0_RTSn 15 14 PA7MFP Alternate Function Setting for PA7MFP 00 GPIO 01 UART0_RX 10 I2C0_SCL 11 SPI1_MISO 13 12 PA6MFP Alte...

Page 41: ...ue SYS_GPB_MFP SYS_BA 0x3C R W GPIOB multiple alternate functions control register 0x0000_0000 31 30 29 28 27 26 25 24 PB15MFP PB14MFP PB13MFP PB12MFP 23 22 21 20 19 18 17 16 PB11MFP PB10MFP PB9MFP PB...

Page 42: ...on Setting for PB10MFP 00 GPIO 10 I2S0_SDI 11 UART1_TX 19 18 PB9MFP Alternate Function Setting for PB9MFP 00 GPIO 01 I2C0_SCL 10 I2S0_BCLK 11 UART1_CTsn 17 16 PB8MFP Alternate Function Setting for PB8...

Page 43: ...DI I GPIOA3 VDD33 SPI0_SSB0 IO SARADC_TRIG I I2S0_SDO O GPIOA4 VDD33 SPI0_MISO0 IO UART0_TX O SPI1_MOSI O GPIOA5 VDD33 SPI0_WP0 MOSI1 IO UART0_RX I SPI1_SCLK O GPIOA6 VDD33 UART0_TX O I2C0_SDA IO SPI1...

Page 44: ...I I CS6 CNP SAR8 GPIOB7 VCCD I2S0_SDO O CS7 C1N SAR9 GPIOB8 VCCD I2C0_SDA I2S0_FS IO UART1_RSTn IO CS8 C2P SAR0 GPIOB9 VCCD I2C0_SCL I2S0_BCLK IO UART1_CTsn IO CS9 SAR1 GPIOB10 VCCD CMP1 O I2S0_SDI I...

Page 45: ...function UNLOCKREG x which will execute this sequence The status of the lock can be determined by reading SYS_REGLCTL bit0 1 is unlocked 0 is locked Once unlocked user can update protected register va...

Page 46: ...to set a workable value before change to use If users wish to change the default frequency it is possible to do so by setting this register A write to FREQ will change the active SYS_OSCTRIMn register...

Page 47: ...set Value SYS_OSC10KTRIM SYS_BA 0x114 R W 10kHz Oscillator LIRC Trim Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 TRMCLK Reserved Reserved 23 22 21 20 19 18 17 16 Reserved TRIM 15 14 13 12 11 10 9 8 T...

Page 48: ...r trim register 0 0xXXXX_XXXX 31 30 29 28 27 26 25 24 EN2MHZ Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TRIM 7 6 5 4 3 2 1 0 TRIM Table 5 13 Oscillator Frequency Adjust Control Re...

Page 49: ...r trim register 1 0xXXXX_XXXX 31 30 29 28 27 26 25 24 EN2MHZ Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TRIM 7 6 5 4 3 2 1 0 TRIM Table 5 14 Oscillator Frequency Adjust Control Re...

Page 50: ...or trim register 2 0xXXXX_XXXX 31 30 29 28 27 26 25 24 EN2MHZ Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TRIM 7 6 5 4 3 2 1 0 TRIM Table 5 15 Oscillator Frequency Adjust Control R...

Page 51: ...24 Reserved XGS 23 22 21 20 19 18 17 16 Reserved SELXT 15 14 13 12 11 10 9 8 Reserved LOWPWR Reserved 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Table 5 16 Xtal Trim Bits Description 31 26 Reserved 2...

Page 52: ...eset Value Reserved SYS_BA 0x128 R W System reserved keep POR value 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserve...

Page 53: ...nter transitions to zero the COUNTFLAG status bit is set The COUNTFLAG bit clears on reads The SYST_CVR value is UNKNOWN on reset Software should write to the register to clear it to zero before enabl...

Page 54: ...imer counted to 0 since last time this register was read 0 Cleared on read or by a write to the Current Value register 1 Set by a count transition from 1 to 0 15 3 Reserved Reserved 2 CLKSRC Clock Sou...

Page 55: ...RVR address 0xE000_E014 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 23 16 15 14 13 12 11 10 9 8 RELOAD 15 8 7 6 5 4 3 2 1 0 RELOAD 7 0 Bits Description 31 24 Reserved Reserved 23 0...

Page 56: ...er SYST_CVR address 0xE000_E018 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 23 16 15 14 13 12 11 10 9 8 CURRENT 15 8 7 6 5 4 3 2 1 0 CURRENT 7 0 Bits Description 31 24 Reserved Re...

Page 57: ...atically save processor state including the registers PC PSR LR R0 R3 R12 to the stack At the end of the ISR the NVIC will restore the above mentioned registers from the stack and resume normal execut...

Page 58: ...mber Interrupt Number Bit in Interrupt Registers Interrupt Name Source IP Interrupt description 0 15 System exceptions 16 0 BOD_IRQn Brown Out Brownout low voltage detector interrupt 17 1 WDT_IRQn WDT...

Page 59: ...8 CAPS_IRQn ANA Capacitive Touch Sensing Relaxation Oscillator Interrupt 45 29 ADC_INT SDADC Audio ADC interrupt 46 30 Reserved 47 31 RTC_INT RTC Real time clock interrupt 5 2 7 2 Vector Table When an...

Page 60: ...red by reset or an exception return Clearing the enable bit prevents new activations of the associated interrupt NVIC interrupts can be pended un pended using a complementary pair of registers to thos...

Page 61: ...000_0000 NVIC_IPR0 SCS_BA 0x300 R W IRQ0 IRQ3 Priority Control Register 0x0000_0000 NVIC_IPR1 SCS_BA 0x304 R W IRQ4 IRQ7 Priority Control Register 0x0000_0000 NVIC_IPR2 SCS_BA 0x308 R W IRQ8 IRQ11 Pri...

Page 62: ...terrupt is not enabled asserting its interrupt signal changes the interrupt state to pending but the NVIC never activates the interrupt regardless of its priority Table 5 24 Interrupt Set Enable Contr...

Page 63: ...Control Register 0x0000_0000 Table 5 25 Interrupt Clear Enable Control Register ICER address 0xE000_E180 Bit Description Bits Description 31 0 CLRENA Clear enable Control Disable one or more interrupt...

Page 64: ...Set Pending Control Register 0x0000_0000 Table 5 26 Interrupt Set Pending Control Register ISPR address 0xE000_E200 Bits Description 31 0 SETPEND Set pending Control Writing 1 to a bit forces pending...

Page 65: ...ar Pending Control Register 0x0000_0000 Table 5 27 Interrupt Clear Pending Control Register ICPR address 0xE000_E280 Bits Description 31 0 CLRPEND Clear pending Control Writing 1 to a bit to clear the...

Page 66: ...2 Reserved 15 14 13 12 11 10 9 8 PRI_1 Reserved 7 6 5 4 3 2 1 0 PRI_0 Reserved Table 5 28 Interrupt Priority Register IPR0 address 0xE000_E400 Bits Description 31 30 PRI_3 Priority of IRQ3 0 denotes t...

Page 67: ...6 Reserved 15 14 13 12 11 10 9 8 PRI_5 Reserved 7 6 5 4 3 2 1 0 PRI_4 Reserved Table 5 29 Interrupt Priority Register IPR1 address 0xE000_E404 Bits Description 31 30 PRI_7 Priority of IRQ7 0 denotes t...

Page 68: ...0 Reserved 15 14 13 12 11 10 9 8 PRI_9 Reserved 7 6 5 4 3 2 1 0 PRI_8 Reserved Table 5 30 Interrupt Priority Register IPR2 address 0xE000_E408 Bits Description 31 30 PRI_11 Priority of IRQ11 0 denotes...

Page 69: ...Reserved 15 14 13 12 11 10 9 8 PRI_13 Reserved 7 6 5 4 3 2 1 0 PRI_12 Reserved Table 5 31 Interrupt Priority Register IPR3 address 0xE000_E40C Bits Description 31 30 PRI_15 Priority of IRQ15 0 denotes...

Page 70: ...Reserved 15 14 13 12 11 10 9 8 PRI_17 Reserved 7 6 5 4 3 2 1 0 PRI_16 Reserved Table 5 32 Interrupt Priority Register IPR4 address 0xE000_E410 Bits Description 31 30 PRI_19 Priority of IRQ19 0 denotes...

Page 71: ...Reserved 15 14 13 12 11 10 9 8 PRI_21 Reserved 7 6 5 4 3 2 1 0 PRI_20 Reserved Table 5 33 Interrupt Priority Register IPR5 address 0xE000_E414 Bits Description 31 30 PRI_23 Priority of IRQ23 0 denotes...

Page 72: ...Reserved 15 14 13 12 11 10 9 8 PRI_25 Reserved 7 6 5 4 3 2 1 0 PRI_24 Reserved Table 5 34 Interrupt Priority Register IPR6 address 0xE000_E418 Bits Description 31 30 PRI_27 Priority of IRQ27 0 denotes...

Page 73: ...Reserved 15 14 13 12 11 10 9 8 PRI_29 Reserved 7 6 5 4 3 2 1 0 PRI_28 Reserved Table 5 35 Interrupt Priority Register IPR7 address 0xE000_E41C Bits Description 31 30 PRI_31 Priority of IRQ31 0 denotes...

Page 74: ...NT_BA 0x1C R IRQ7 Reserved Interrupt Source Identity Register 0xXXXX_XXXX IRQ8_SRC INT_BA 0x20 R IRQ8 TMR0 Interrupt Source Identity Register 0xXXXX_XXXX IRQ9_SRC INT_BA 0x24 R IRQ9 TMR1 Interrupt Sou...

Page 75: ...INT_BA 0x6C R IRQ27 I2S0 Interrupt Source Identity Register 0xXXXX_XXXX IRQ28_SRC INT_BA 0x70 R IRQ28 CAPS Interrupt Source Identity Register 0xXXXX_XXXX IRQ29_SRC INT_BA 0x74 R IRQ29 ADC Interrupt S...

Page 76: ...egister Offset R W Description Reset Value IRQ0_SRC INT_BA 0x00 R IRQ0 BOD Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 77: ...egister Offset R W Description Reset Value IRQ1_SRC INT_BA 0x04 R IRQ1 WDT Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 78: ...egister Offset R W Description Reset Value IRQ2_SRC INT_BA 0x08 R IRQ2 EINT0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 1...

Page 79: ...egister Offset R W Description Reset Value IRQ3_SRC INT_BA 0x0C R IRQ3 EINT1 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 1...

Page 80: ...ster Offset R W Description Reset Value IRQ4_SRC INT_BA 0x10 R IRQ4 GPA B Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 1...

Page 81: ...egister Offset R W Description Reset Value IRQ5_SRC INT_BA 0x14 R IRQ5 ALC Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 82: ...egister Offset R W Description Reset Value IRQ6_SRC INT_BA 0x18 R IRQ6 PWM0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 83: ...egister Offset R W Description Reset Value IRQ8_SRC INT_BA 0x20 R IRQ8 TMR0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 84: ...egister Offset R W Description Reset Value IRQ9_SRC INT_BA 0x24 R IRQ9 TMR1 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 85: ...Offset R W Description Reset Value IRQ11_SRC INT_BA 0x2C R IRQ11 UART1 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 86: ...gister Offset R W Description Reset Value IRQ12_SRC INT_BA 0x30 R IRQ12 UART0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 87: ...Offset R W Description Reset Value IRQ13_SRC INT_BA 0x34 R IRQ13 SPI1 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 1...

Page 88: ...egister Offset R W Description Reset Value IRQ14_SRC INT_BA 0x38 R IRQ14 SPI0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 89: ...r Offset R W Description Reset Value IRQ15_SRC INT_BA 0x3C R IRQ15 DPWM Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 90: ...egister Offset R W Description Reset Value IRQ18_SRC INT_BA 0x48 R IRQ18 I2C0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 91: ...egister Offset R W Description Reset Value IRQ21_SRC INT_BA 0x54 R IRQ21 CMP Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 1...

Page 92: ...Offset R W Description Reset Value IRQ22_SRC INT_BA 0x58 R IRQ22 MAC Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Page 93: ...gister Offset R W Description Reset Value IRQ25_SRC INT_BA 0x64 R IRQ25 SARADC Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 94: ...egister Offset R W Description Reset Value IRQ26_SRC INT_BA 0x68 R IRQ26 PDMA Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 95: ...egister Offset R W Description Reset Value IRQ27_SRC INT_BA 0x6C R IRQ27 I2S0 Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 96: ...egister Offset R W Description Reset Value IRQ28_SRC INT_BA 0x70 R IRQ28 CAPS Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 97: ...egister Offset R W Description Reset Value IRQ29_SRC INT_BA 0x74 R IRQ29 ADC Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 1...

Page 98: ...egister Offset R W Description Reset Value IRQ31_SRC INT_BA 0x7C R IRQ31 RTC Interrupt Source Identity Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 1...

Page 99: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 IRQ_TM Reserved NMI_SEL 4 0 Bits Description 31 7 Reserved Reserved 7 IRQ_TM IRQ Test Mode If set to 1 then peripheral IRQ signals...

Page 100: ...TMR0 7 6 5 4 3 2 1 0 Reserved PWM0 ALC GPAB EINT1 EINT0 WDT BOD Bits Description 31 RTC IRQ31 RTC Interrupt Source Identity Register 0 No effect 1 clear the interrupt 30 Reserved IRQ30 RESERVED Interr...

Page 101: ...ster 0 No effect 1 clear the interrupt 17 Reserved IRQ17 RESERVED Interrupt Source Identity Register 16 Reserved IRQ16 RESERVED Interrupt Source Identity Register 15 DPWM IRQ15 DPWM Interrupt Source I...

Page 102: ...5 ALC IRQ5 ALC Interrupt Source Identity Register 0 No effect 1 clear the interrupt 4 GPAB IRQ4 GPA B Interrupt Source Identity Register 0 No effect 1 clear the interrupt 3 EINT1 IRQ3 EINT1 Interrupt...

Page 103: ...set Value SYSINFO Base Address SYSINFO_BA 0xE000_ED00 SYSINFO_CPUID SYSINFO_BA 0x000 R CPUID Base Register 0x410C_C200 SYSINFO_ICSR SYSINFO_BA 0x004 R W Interrupt Control State Register 0x0000_0000 SY...

Page 104: ...PUID Base Register 0x410C_C200 31 30 29 28 27 26 25 24 IMPCODE 23 22 21 20 19 18 17 16 Reserved PART 15 14 13 12 11 10 9 8 PARTNO 11 4 7 6 5 4 3 2 1 0 PARTNO 3 0 REVISION Bits Description 31 24 IMPCOD...

Page 105: ...Reserved 28 PPSVISET Set a Pending PendSV Interrupt This is normally used to request a context switch Reads back with current state 1 if Pending 0 if not 27 PPSVICLR Clear a Pending PendSV Interrupt...

Page 106: ...ISD91200 Series Technical Reference Manual Release Date Sep 16 2019 106 Revision 2 4 8 0 VTACT Vector Active 0 Thread mode Value 1 the exception number for the current executing exception...

Page 107: ...Description 31 16 VTKEY Vector Key The value 0x05FA must be written to this register otherwise a write to register is UNPREDICTABLE 15 ENDIANES Endianness Read Only Reads 0 indicating little endian ma...

Page 108: ...ctive to Pending are included in the list of wakeup events for the WFE instruction When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is...

Page 109: ...Reset Value SYSINFO_SHPR2 SYSINFO_BA 0x01C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7...

Page 110: ...riority Register 3 0x0000_0000 31 30 29 28 27 26 25 24 PRI15 Reserved 23 22 21 20 19 18 17 16 PRI14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI15 Priori...

Page 111: ...ter these various modes by requesting a power mode then requesting the Cortex M0 to execute the WFI or the WFE instruction 5 3 1 Clock Generator The clock generator consists of 4 sources listed below...

Page 112: ...ed by HCLKDIV 1 to produce the master clock for the device 010 001 000 LIRC LXT HIRC CLK_CLKSEL0 HCLKSEL 1 HCLKDIV 1 CLK_CLKDIV0 HCLKDIV 011 HXT HCLK CPUCLK PCLK CPU AHB APB Figure 5 4 System Clock Bl...

Page 113: ...t can be interrogated to allow software to determine that previous state was a DPD state In DPD there are three ways to wake up the device 1 A high to low transition on the WAKEUP pin 2 A timed wakeup...

Page 114: ...PWRSTSF SPDF To enter the SPD state the user must set the register bit CLK_PWRCTL SPDEN then execute a WFI or WFE instruction Note that when debug interface is active device will not enter SPD Also on...

Page 115: ...Sleep mode Using this mode power consumption can be minimized while waiting for events such as a PDMA operation collecting data from the ADC once PDMA has finished the core can be woken up to process...

Page 116: ...Reserved HXTEN LIRCEN HIRCEN LXTEN Reserved Table 5 37 System Power Control Register CLK_PWRCTL address 0x5000_0200 Bit Description Bits Description 31 27 Reserved Reserved 27 WKPUEN Wakeup Pin Pull...

Page 117: ...e 1 to this bit to release IO state after exiting SPD if hold request was made with the HOLD_IO bit 12 HOLDIO When entering SPD mode IO state is automatically held If this bit is set to 1 then this sa...

Page 118: ..._AHBCLK CLK_BA 0x04 R W AHB Device Clock Enable Control Register 0x0000_0005 7 6 5 4 3 2 1 0 Reserved ISPCKEN PDMACKEN HCLKEN Table 5 38 AHB Device Clock Enable Register CLK_AHBCLK address 0x5000_0204...

Page 119: ...22 21 20 19 18 17 16 Reserved PWM0CH23C KEN PWM0CH01C KEN Reserved BIQALCKEN SARADCKEN UART0CKEN 15 14 13 12 11 10 9 8 UART1CKEN Reserved DPWMCKEN SPI0CKEN SPI1CKEN Reserved I2C0CKEN 7 6 5 4 3 2 1 0...

Page 120: ...Enable 14 Reserved 13 DPWMCKEN Differential PWM Speaker Driver Clock Enable Control 0 Disable 1 Enable 12 SPI0CKEN SPI0 Clock Enable Control 0 Disable 1 Enable 11 SPI1CKEN SPI1 Clock Enable Control 0...

Page 121: ...ue will be latched in to the CLK_DPDSTATE register on next DPD event Register Offset R W Description Reset Value CLK_DPDSTATE CLK_BA 0x0C R W Deep Power Down State Register 0x0000_XX00 31 30 29 28 27...

Page 122: ...Trim for 32 768MHz selected 10 Trim for reserved 5 3 STCLKSEL MCU Cortex_M0 SYST Clock Source Select These bits are protected to write to bits first perform the unlock sequence 000 clock source from L...

Page 123: ...served SARADCSEL 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved TMR1SEL Reserved TMR0SEL 7 6 5 4 3 2 1 0 Reserved DPWMSEL ADCSEL WDTSEL Table 5 42 Clock Source Select Register 1 CLK_C...

Page 124: ...T 010 clock source from HXT 011 clock source from external pin GPIOA 10 1xx clock source from internal HCLK default 7 6 Reserved 5 4 DPWMSEL Differential Speaker Driver PWM Clock Source Select 00 cloc...

Page 125: ...ce The SARADC clock frequency ADC clock source frequency SARADCDIV 1 23 16 SDADCDIV SDADC Clock Divide Number From ADC Clock Source The SDADC clock frequency SDADC clock source frequency SDADCDIV 1 15...

Page 126: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved UART1DIV 7 6 5 4 3 2 1 0 Reserved I2S0SEL Table 5 44 Clock Source Select Control Register 2 CLK_CLKSEL2 address 0x5000_02...

Page 127: ...FF 31 30 29 28 27 26 25 24 Reserved ANACKEN I2SCKEN SDADCCKEN Reserved Reserved Reserved Reserved 23 22 21 20 19 18 17 16 Reserved Reserved PWM0CH23C KEN PWM0CH01C KEN Reserved BQALCKEN SARADCCKE N UA...

Page 128: ...aker Driver Sleep Clock Enable Control 0 Disable 1 Enable 12 SPI0CKEN SPI0 Sleep Clock Enable Control 0 Disable 1 Enable 11 SPI1CHEN SPI1 Sleep Clock Enable Control 0 Disable 1 Enable 10 9 Reserved 8...

Page 129: ...eference Manual Release Date Sep 16 2019 129 Revision 2 4 1 PDMACKEN PDMA Controller Sleep Clock Enable Control 0 Disable 1 Enable 0 HCLKCKEN CPU Clock Sleep Enable HCLK Must be left as 1 for normal o...

Page 130: ...ved SPDF STOPF DSF Table 5 46 Power State Flag Register CLK_PWRSTSF address 0x5000_0224 Bit Description Bits Description 31 3 Reserved 2 SPDF Powered Down Flag This flag is set if core logic was power...

Page 131: ...ble Register 0x0000_00XX 7 6 5 4 3 2 1 0 ICEDATST ICECLKST Reserved DISPDREQ Table 5 47 Debug Power Down Register CLK_DBGPD address 0x5000_0228 Bit Description Bits Description 7 ICEDATST ICEDATST Pin...

Page 132: ...MRSTS 15 14 13 12 11 10 9 8 Reserved SELWKTMR 7 6 5 4 3 2 1 0 SELWKTMR Table 5 48 Deep Power Down 10K Wakeup Timer CLK_WAKE10K address 0x5000_022C Bit Description Bits Description 31 WAKE10KEN Enable...

Page 133: ...dge sensitive inputs can also be de bounced In quasi bidirectional mode each GPIO pin has a weak pull up resistor which is approximately 110K 300K for VDD from 5 0V to 2 4V Each pin can generate and i...

Page 134: ...and the I O pin supports digital output and input function where the source current is only between 30 200uA Before input function is performed the corresponding bit in Px_DOUT must be set to 1 The qu...

Page 135: ...0000 PA_INTEN GPIO_BA 0x01C R W GPIO Port A Interrupt Enable 0x0000_0000 PA_INTSRC GPIO_BA 0x020 R W GPIO Port A Interrupt Source Flag 0x0000_0000 PB_MODE GPIO_BA 0x040 R W GPIO Port B Pin I O Mode Co...

Page 136: ...e Control 0xFFFF_FFFF Table 5 49 GPIO Mode Control Register 31 30 29 28 27 26 25 24 MODE15 MODE14 MODE13 MODE12 23 22 21 20 19 18 17 16 MODE11 MODE10 MODE9 MODE8 15 14 13 12 11 10 9 8 MODE7 MODE6 MODE...

Page 137: ...00_0000 PB_DINOFF GPIO_BA 0x044 R W GPIO Port B Pin Input Disable 0x0000_0000 Table 5 50 GPIO Input Disable Register 31 30 29 28 27 26 25 24 DINOFF 31 24 23 22 21 20 19 18 17 16 DINOFF 23 16 15 14 13...

Page 138: ...Data Output Register Px_DOUT 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DOUT 15 8 7 6 5 4 3 2 1 0 DOUT 7 0 Bits Description 31 16 Reserved Reserved 15 0 DO...

Page 139: ...00 Table 5 52 GPIO Data Output Write Mask Register Px_DATMSK 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DATMSK 15 8 7 6 5 4 3 2 1 0 DATMSK 7 0 Bits Descrip...

Page 140: ...Value 0x0000_XXXX PB_PIN GPIO_BA 0x050 R GPIO Port B Pin Value 0x0000_XXXX Table 5 53 GPIO PIN Value Register Px_PIN 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Page 141: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DBEN 15 8 7 6 5 4 3 2 1 0 DBEN 7 0 Bits Description 31 16 Reserved Reserved 15 0 DBEN Port A B De bounce Enable Control DBEN n used to enable the de bo...

Page 142: ...14 13 12 11 10 9 8 TYPE 15 8 7 6 5 4 3 2 1 0 TYPE 7 0 Bits Description 31 16 Reserved Reserved 15 0 TYPE Port A B Edge or Level Detection Interrupt Trigger Type TYPE n used to control whether the int...

Page 143: ...rate an interrupt If the interrupt is configured in edge trigger mode a state change from low to high will generate an interrupt GPB 0 and GPB 1 trigger individual IRQ vectors IRQ2 IRQ3 while remainin...

Page 144: ...Flag 0x0000_0000 PB_INTSRC GPIO_BA 0x060 R W GPIO Port B Interrupt Source Flag 0x0000_0000 Table 5 57 GPIO Interrupt Source Flag Register Px_INTSRC 15 14 13 12 11 10 9 8 INTSRC 15 8 7 6 5 4 3 2 1 0 I...

Page 145: ...s bit 0 will gate the clock to the interrupt generation circuit if the GPIOx n interrupt is disabled 0 disable the clock if the GPIOx n interrupt is disabled 1 Interrupt generation clock always active...

Page 146: ...de where detection can be set up to be active for a configurable on and off time BOD operation require that the OSC10k low power oscillator is enabled CLK_PWRCTL LIRCDPDEN 0 5 5 1 Brownout Register Ma...

Page 147: ..._BA 0x00 R W Brown Out Detector Select Register 0x0000_0000 Table 5 59 Brownout Detector Select Register BOD_BODSEL address 0x4008_4000 7 6 5 4 3 2 1 0 Reserved BODHYS BODVL Bits Description 31 5 Rese...

Page 148: ...14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BODRST BODOUT BODIF BODINTEN BODEN Bits Description 31 5 Reserved Reserved 18 17 LVR_FILTER 00 LVR output will be filtered by 1 HCLK 01 LVR output...

Page 149: ...ep 16 2019 149 Revision 2 4 2 BODINTEN BOD Interrupt Enable 0 Disable BOD Interrupt 1 Enable BOD Interrupt 1 0 BODEN BOD Enable 1xb Enable continuous BOD detection 01b Enable time multiplexed BOD dete...

Page 150: ...served 19 16 DURTON Time BOD Detector Is Active DURTON 1 100us Minimum value is 1 default is 400us 15 0 DURTOFF Time BOD Detector Is Off DURTOFF 1 100us Minimum value is 7 default is 99 6ms 5 6 I2C Se...

Page 151: ...the bus are Master Slave up to 1Mbit s Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corrup...

Page 152: ...owledged by the slave the transfer direction is changed and slave sends data to the master and master acknowledges the data transfer 1 read data transfer n bytes acknowledge S SLAVE ADDRESS R W A DATA...

Page 153: ...nowledge bit by pulling the SDA low at the 9th SCL clock cycle 5 6 1 5 Data Transfer Once successful slave addressing has been achieved the data transfer can proceed on a byte by byte basis in the dir...

Page 154: ...y W in the flow diagrams Thus the first byte transmitted is SLA W Serial data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions ar...

Page 155: ...fers in each mode are shown in the following figures Legend for the following five figures 08H A START has been transmitted STA STO SI AA 0 0 0 X SLA W will be transmitted ACK bit will be received 18H...

Page 156: ...I AA 1 1 1 X A STOP followed by a START will be transmitted STO flag will be reset Send a STOP followed by a START 28H Data byte in S1DAT has been transmitted ACK has been received or 30H Data byte in...

Page 157: ...ill be returned 10H A repeated START has been transmitted STA STO SI AA 0 0 1 X SLA R will be transmitted ACK bit will be transmitted SIO1 will be switched to MST REC mode STA STO SI AA 1 0 1 X A STAR...

Page 158: ...een transmitted ACK has been received STA STO SI AA 1 0 1 0 Switch to not addressed SLV mode No recognition of own SLA A START will be transmitted when the becomes free STA STO SI AA 0 0 1 1 Switch to...

Page 159: ...Previously addressed with own SLA address NOT ACK has been returned STA STO SI AA 1 0 1 0 Switch to not addressed SLV mode No recognition of own SLA A START will be transmitted when the becomes free...

Page 160: ...becomes free 98H Previously addressed with General Call Data byte has been received NOT ACK has been returned STA STO SI AA 1 0 1 0 Switch to not addressed SLV mode No recognition of own SLA A START...

Page 161: ...ve mode it can be received the general call address by 00H after Master send general call address to I2C bus then it will follow status of GC mode If it is in master mode the AA bit I2C_CTL 2 Assert A...

Page 162: ...d an acknowledged low level to SDA will be returned during the acknowledge clock pulse on the SCL line when 1 A slave is acknowledging the address sent from master 2 A receiver device is acknowledging...

Page 163: ...he time out counter is enabled the counter starts up counting until it overflows TOIF 1 and generates I2C interrupt to CPU or stops counting by clearing TOCEN to 0 When time out counter is enabled set...

Page 164: ...Register 0x0000_00F8 I2C_CLKDIV I2C_BA 0x10 R W I2C clock divided Register 0x0000_0000 I2C_TOCTL I2C_BA 0x14 R W I2C Time out control Register 0x0000_0000 I2C_ADDR1 I2C_BA 0x18 R W I2C Slave address...

Page 165: ...ndition is detected this bit will be cleared by hardware automatically In slave mode setting STO resets I2C hardware to the defined not addressed slave mode This means it is NO LONGER in the slave rec...

Page 166: ...n Reset Value I2C_DAT I2C_BA 0x08 R W I2C DATA Register 0x0000_0000 7 6 5 4 3 2 1 0 DAT 7 0 Bits Description 31 8 Reserved Reserved 7 0 DAT I2C Data Register During master or slave transmit mode data...

Page 167: ...ere are 26 possible status codes When I2C_STATUS contains F8H no serial interrupt is requested All other I2C_STATUS values correspond to defined I2C states When each of these states is entered a statu...

Page 168: ...ROL REGISTER I2C_CLKDIV Register Offset R W Description Reset Value I2C_CLKDIV I2C_BA 0x10 R W I2C clock divided Register 0x0000_0000 7 6 5 4 3 2 1 0 DIVIDER 7 0 Bits Description 31 8 Reserved Reserve...

Page 169: ...F Bits Description 31 3 Reserved Reserved 2 TOCEN Time out Counter Control Bit 0 Disable 1 Enable When enabled the 14 bit time out counter will start counting when SI is clear Setting flag SI to high...

Page 170: ...W I2C Slave address Register2 0x0000_0000 I2C_ADDR3 I2C_BA 0x20 R W I2C Slave address Register3 0x0000_0000 7 6 5 4 3 2 1 0 ADDR 7 1 GC Bits Description 31 8 Reserved Reserved 7 1 ADDR I2C Address Reg...

Page 171: ...SK2 I2C_BA 0x2C R W I2C Slave address Mask Register2 0x0000_0000 I2C_ADDRMSK3 I2C_BA 0x30 R W I2C Slave address Mask Register3 0x0000_0000 7 6 5 4 3 2 1 0 ADDRMSK Reserved Bits Description 31 8 Reserv...

Page 172: ...upt request is generated If PWM timer is configured in continuous mode when the down counter reaches zero it is reloaded with PWM Counter Register automatically and begins decrementing again If the PW...

Page 173: ...sion 2 4 5 7 2 2 Capture Function Features Timing control logic shared with PWM Generators 2 Capture input channels shared with 2 PWM output channels Each channel supports a rising latch register RCAP...

Page 174: ...0 1 0 DZI01 DZEN01 CH0INV CH1INV PWMIE0 PWMIF0 PWMIE1 PWMIF1 Clock Divider CNR1 CMR1 PCR CNR0 CMR0 PCR PWM0CH01_CLK from clock controller POE PWM0 PA 12 PWM0 PA 13 PWM1 POE PWM1 Figure 5 25 PWM Gener...

Page 175: ...5 27 PWM Timer Operation Timing First initialize the PWM settings At the same time ensure that GPIO are configured to PWM function Next step is to enable PWM channel After this if PERIOD or CMP regis...

Page 176: ...to PWM counter when PWM counter reaches zero If PERIODx is set to zero PWM counter will halt when PWM counter counts to zero If CNTMODEx is set as zero counter will stop immediately PWM Waveform write...

Page 177: ...ection The function generates a programmable time gap between rising PWM outputs The user can program PPRx DZI to determine the Dead Zone interval The Dead Zone generator behavior is demonstrated in F...

Page 178: ...annel 1 has the same feature by setting PWM_CAPCTL01 17 and PWM_CAPCTL01 18 Whenever the Capture module issues a capture interrupt the corresponding PWM counter will be reloaded with PERIODx at this m...

Page 179: ...rescaler PWM_CLKPSC 3 Setup inverter on off dead zone generator on off auto reload one shot mode and Stop PWM timer PWM_CTL 4 Setup comparator register PWM_CMPDAT to set PWM duty cycle 5 Setup PWM dow...

Page 180: ...IV 2 Setup prescaler PWM_CLKPSC 3 Setup channel enable rising falling interrupt enable and input signal inverter on off PWM_CAPCTL01 PWM_CAPCTL23 4 Setup PWM down counter PERIOD 5 Set Capture Input En...

Page 181: ...2 PWM_BA 0x02C R PWM Data Register 2 0x0000_0000 PWM_PERIOD3 PWM_BA 0x030 R W PWM Counter Register 3 0x0000_0000 PWM_CMPDAT3 PWM_BA 0x034 R W PWM Comparator Register 3 0x0000_0000 PWM_CNT3 PWM_BA 0x03...

Page 182: ...ep 16 2019 182 Revision 2 4 PWM_FCAPDAT3 PWM_BA 0x074 R Capture Falling Latch Register Channel 3 0x0000_0000 PWM_CAPINEN PWM_BA 0x078 R W Capture Input Enable Register 0x0000_0000 PWM_POEN PWM_BA 0x07...

Page 183: ...d PWM0CH3 These 8 bits determine dead zone length The unit time of dead zone length is that from clock selector 0 23 16 DTCNT01 Dead Zone Interval Register for Pair of PWM0CH0 and PWM0CH1 These 8 bits...

Page 184: ...3 2 1 0 Reserved CLKDIV1 Reserved CLKDIV0 Table 5 63 PWM Clock Select Register PWM_CLKDIV address 0x4004_0004 Bits Description 31 15 Reserved Reserved 14 12 CLKDIV3 Timer 3 Clock Source Selection Tabl...

Page 185: ...1 28 Reserved Reserved 27 CNTMODE3 PWM timer 3 Auto reload One shot Mode 0 One Shot Mode 1 Auto load Mode Note A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared 26 P...

Page 186: ...nable Disable Pair of PWM0CH2 and PWM0CH3 0 Disable 1 Enable Note When Dead Zone Generator is enabled the pair of PWM0CH2 and PWM0CH3 become a complementary pair 4 DTEN01 Dead zone 01 Generator Enable...

Page 187: ...28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PERIOD 15 8 7 6 5 4 3 2 1 0 PERIOD 7 0 Table 5 65 PWM Counter Register PWM_PERIODx address 0x4004_00C C x Bits Descripti...

Page 188: ...0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMP 15 8 7 6 5 4 3 2 1 0 CMP 7 0 Table 5 66 PWM Comparator Register PWM_CMPDATx address 0x4004_0010 C x Bit...

Page 189: ...0000 PWM_CNT1 PWM_BA 0x020 R PWM Data Register 1 0x0000_0000 PWM_CNT2 PWM_BA 0x02C R PWM Data Register 2 0x0000_0000 PWM_CNT3 PWM_BA 0x038 R PWM Data Register 3 0x0000_0000 15 14 13 12 11 10 9 8 CNT 1...

Page 190: ...nable Register 0x0000_0000 7 6 5 4 3 2 1 0 Reserved PIEN3 PIEN2 PIEN1 PIEN0 Table 5 68 PWM Interrupt Enable Register PWM_INTEN address 0x4004_0040 Bits Description 31 4 Reserved Reserved 3 PIEN3 PWM T...

Page 191: ...is set by hardware when PWM0CH3 down counter reaches zero software can clear this bit by writing 1 to it 2 PIF2 PWM Timer 2 Interrupt Flag Flag is set by hardware when PWM0CH2 down counter reaches ze...

Page 192: ...down counter and this bit is set by hardware software can clear this bit by writing a zero to it 20 CAPIF1 Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt is enabled CRLIEN1 1 a...

Page 193: ...esult in CAPIF0 to high Similarly a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled CFLIEN0 1 This flag is cleared by software writing a 1 to it 3 C...

Page 194: ...n input channel 3 has a rising transition PWM_RCAPDAT3 was latched with the value of PWM down counter and this bit is set by hardware software can clear this bit by writing a zero to it 21 Reserved Re...

Page 195: ...on Flag If channel 2 rising latch interrupt is enabled CRLIEN2 1 a rising transition at input channel 2 will result in CAPIF2 to high Similarly a falling transition will cause CAPIF2 to be set high if...

Page 196: ...nnel 1 0x0000_0000 PWM_RCAPDAT2 PWM_BA 0x068 R Capture Rising Latch Register Channel 2 0x0000_0000 PWM_RCAPDAT3 PWM_BA 0x070 R Capture Rising Latch Register Channel 3 0x0000_0000 15 14 13 12 11 10 9 8...

Page 197: ...nel 1 0x0000_0000 PWM_FCAPDAT2 PWM_BA 0x06C R Capture Falling Latch Register Channel 2 0x0000_0000 PWM_FCAPDAT3 PWM_BA 0x074 R Capture Falling Latch Register Channel 3 0x0000_0000 15 14 13 12 11 10 9...

Page 198: ...able Register PWM_CAPINEN address 0x4004_0078 Bits Description 31 4 Reserved Reserved 3 0 CAPINEN Capture Input Enable Register 0 OFF GPA 13 12 GPB 15 14 pin input disconnected from Capture block 1 ON...

Page 199: ...put to pin Note The corresponding GPIO pin also must be switched to PWM function refer to SYS_GPA_MFP 2 POEN2 PWM0CH2 Output Enable Register 0 Disable PWM0CH2 output to pin 1 Enable PWM0CH2 output to...

Page 200: ...period options 1 128 1 64 1 32 1 16 1 8 1 4 1 2 and 1 second which are selected by RTC_TICK TTR When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting registers RTC_TALM and RTC_CALM the...

Page 201: ...er written data is out of bounds for a valid BCD time or calendar load RTC does not check validity of RTC_WEEKDAY and RTC_CAL write either 5 8 3 2 RTC Initiation When RTC block is powered on programme...

Page 202: ...time scale selection depends on RTC_CLKFMT 24HEN 5 8 3 7 Day of the week counter The RTC unit provides day of week in Day of the Week Register RTC_WEEKDAY The value is defined from 0 to 6 to represent...

Page 203: ...C_TALM 00 00 00 hour minute second RTC_CLKFMT 1 24 hr mode RTC_WEEKDAY 6 Saturday RTC_INTEN 0 RTC_INTSTS 0 RTC_LEAPYEAR 0 RTC_TICK 0 PWRTOUT 5555 4 In RTC_TIME and RTC_TALM only 2 BCD digits are used...

Page 204: ...0x0000_0700 RTC_TIME RTC_BA 0x00C R W Time Load Register 0x0000_0000 RTC_CAL RTC_BA 0x010 R W Calendar Load Register 0x0000_0000 RTC_CLKFMT RTC_BA 0x014 R W Time Scale Selection Register 0x0000_0001...

Page 205: ...27 26 25 24 INIT 23 22 21 20 19 18 17 16 INIT 15 14 13 12 11 10 9 8 INIT 7 6 5 4 3 2 1 0 INIT ATVSTS Table 5 77 RTC Initialization Register RTC_INIT address 0x4000_8000 Bits Description 31 1 INIT RTC...

Page 206: ...cess Enable Flag Read Only 1 RTC register read write enable 0 RTC register read write disable This bit will be set after RWEN 15 0 register is set to 0xA965 it will clear automatically in 512 RTC cloc...

Page 207: ...1 0 Reserved FRACTION Table 5 80 RTC Frequency Compensation Register RTC_FREQADJ address 0x4000_8008 Bits Description 31 12 Reserved Reserved 11 8 INTEGER Integer Part Register should contain the val...

Page 208: ...7 16 Reserved TENHR HR 15 14 13 12 11 10 9 8 Reserved TENMIN MIN 7 6 5 4 3 2 1 0 Reserved TENSEC SEC Table 5 81 RTC Time Load Register RTC_TIME address 0x4000_800C Bits Description 31 22 Reserved Rese...

Page 209: ...0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 TENYEAR YEAR 15 14 13 12 11 10 9 8 Reserved TENMON MON 7 6 5 4 3 2 1 0 Reserved TENDAY DAY Table 5 82 RTC Calendar Load Register R...

Page 210: ...4 3 2 1 0 Reserved 24HEN Bits Description 31 1 Reserved Reserved 0 24HEN 24 hour 12 hour Mode Selection Determines whether RTC_TIME and RTC_TALM are in 24 hour mode or 12 hour mode 1 select 24 hour ti...

Page 211: ...R W Description Reset Value RTC_WEEKDAY RTC_BA 0x018 R W Day of the Week Register 0x0000_0000 7 6 5 4 3 2 1 0 Reserved WEEKDAY Table 5 84 RTC Day of Week Register RTC_WEEKDAY address 0x4000_8018 Bits...

Page 212: ...ister RTC_TALM address 0x4000_801C Bits Description 31 22 Reserved Reserved 21 20 TENHR 10 Hour Time Digit of Alarm Setting 0 3 2 19 16 HR 1 Hour Time Digit of Alarm Setting 0 9 15 Reserved Reserved 1...

Page 213: ...CALM address 0x4000_8020 Bits Description 31 24 Reserved Reserved 23 20 TENYEAR 10 Year Calendar Digit of Alarm Setting 0 9 19 16 YEAR 1 Year Calendar Digit of Alarm Setting 0 9 15 13 Reserved Reserve...

Page 214: ...scription Reset Value RTC_LEAPYEAR RTC_BA 0x024 R Leap year Indicator Register 0x0000_0000 7 6 5 4 3 2 1 0 Reserved LEAPYEAR Table 5 87 RTC Leap Year Indicator Register RTC_LEAPYEAR address 0x4000_802...

Page 215: ...Enable Register 0x0000_0000 7 6 5 4 3 2 1 0 Reserved TICKIEN ALMIEN Table 5 88 RTC Interrupt Enable Register RTC_INTEN address 0x4000_8028 Bits Description 31 2 Reserved Reserved 1 TICKIEN Time tick...

Page 216: ...Flag When RTC Time Tick Interrupt is enabled RTC_INTEN TICKIF 1 RTC unit will set TIF high at the rate selected by RTC_TICK 2 0 This bit cleared acknowledged by writing 1 to it 0 Indicates no Time Ti...

Page 217: ...ck Register RTC_TICK address 0x4000_8030 Bits Description 31 4 Reserved Reserved 3 TWKEN RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power down mode when a RTC Time Tick o...

Page 218: ...s lines to access two slave devices it also can be set as a slave controlled by an off chip master device In addition the SPI0 interface supports Dual and Quad IO as is common on serial flash memories...

Page 219: ...e SPI serial clock rate of the master device The frequency of SPI engine clock cannot be faster than the APB clock rate regardless of Master or Slave mode 5 9 4 2 Master Slave Mode This SPI0 controlle...

Page 220: ...transactions In Slave mode to recognize the inactive state of the slave select signal the inactive period of the slave select signal must be larger than or equal to 3 engine clock periods between two...

Page 221: ...APB access to the SPI controller is via the 32bit wide TX and RX registers When the transfer is set as MSB first SPI0_CTL LSB 0 and the SPI0_CTL REORDER bit is set the data stored in the TX buffer and...

Page 222: ...0x02 0x03 0x04 0x05 0x06 0x07 0x08 unsigned int uiSPI_DATA 0x01020304 0x05060708 ucSPI_DATA uiSPI_DATA RAM Address RAM Contents 7 0 31 24 23 16 15 8 APB Data Bus Byte0 Byte3 Byte2 Byte1 Byte0 Byte3 By...

Page 223: ...and SSINAIF will be set to 1 when the SPIEN and SLAVE bits were set to 1 and slave senses the slave select signal active or inactive The SPI controller will issue an interrupt if the SSINAIEN or SSACT...

Page 224: ...FIFO mode if the valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH the transmit FIFO interrupt flag will be set to 1 The SPI controller will generate a tr...

Page 225: ...SPI_CLK SPI_SS CLKP 0 CLKP 1 SS_LVL 0 SS_LVL 1 SPI_MOSI0 SPI_MISO0 TX0 30 TX0 16 TX0 15 TX0 14 LSB TX0 0 RX0 30 RX0 16 RX0 14 LSB RX0 0 MSB RX0 31 RX0 15 MSB TX0 31 SPI_MOSI1 SPI_MISO1 TX1 30 TX1 16...

Page 226: ...as the odd bit data output If the DUALIOEN is set as 1 and QDIODIR is set as 0 both the SPI0_MISO0 and SPI0_MOSI0 will be set as data input ports SPI_SS 7 6 5 4 3 2 1 0 SPI_CLK SPI_MOSI SPI_MISO DUAL...

Page 227: ...2 6 2 6 2 7 3 7 3 7 3 Output Output CS CLK DI IO0 DO IO1 WP IO2 HOLD IO3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 Figure 5 46 Bit Sequence of Quad Output Mode 5...

Page 228: ...MISO Pin in Slave Mode MISO Pin in Master Mode or MOSI Pin in Slave Mode SPI_TX Buffer Transmit Buffer 0 Receive Buffer 0 SPI_RX Buffer APB Write Read 1 2 n 1 2 n Figure 5 47 FIFO Mode Block Diagram I...

Page 229: ...after one transaction done or the SLVTOCNT is set to 0 If the value of the time out counter greater or equal than the value of SLVTOCNT before one transaction done the slave time out event occurs abd...

Page 230: ...CNTRL CLKP 0 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 Figure 5 48 SPI Timing in Master Mode SPICLK MISO Master Mode CNTRL SLVAE 0 CNTRL LSB 1 CNTRL Tx_NUM 0x0 CNT...

Page 231: ...1 CNTRL CLKP 0 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 Figure 5 50 SPI Timing in Slave Mode SPICLK MOSI Slave Mode CNTRL SLVAE 1 CNTRL LSB 1 CNTRL Tx_NUM 0x01 CNT...

Page 232: ...so that data changes on falling edge of SCLK set SPI0_CTL RXNEG 0 so that data is latched into device on positive edge of SCLK set SPI0_CTL DWIDTH 4 and SPI0_CTL TX_NUM 0 for a single byte transfer an...

Page 233: ...WIDTH 4 and SPI0_CTL TX_NUM 0 for a single byte transfer and finally set SPI0_CTL LSB 1 for LSB first transfer 3 If SPI slave is to transmit one byte of data to the off chip master device write first...

Page 234: ...Master Only 0x0000_0000 SPI0_SSCTL SPI0_BA 0x08 R W Slave Select Register 0x0000_0000 SPI0_PDMACTL SPI0_BA 0x0C R W SPI PDMA Control Register 0x0000_0000 SPI0_FIFOCTL SPI0_BA 0x10 R W FIFO Control St...

Page 235: ...ion 31 25 Reserved Reserved 24 RXMODEEN FIFO Receive Mode Enable 0 Disable function 1 Enable FIFO receive mode In this mode SPI transactions will be continuously performed while RXFULL is not active T...

Page 236: ...ransfer mode 1 Enable two bit transfer mode When 2 bit mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the seco...

Page 237: ...SPICLK clock cycle SUSPITV 0xE 14 5 SPICLK clock cycle SUSPITV 0xF 15 5 SPICLK clock cycle Note For DUAL and QUAD transactions with SUSPITV must be set to 0 3 CLKPOL Clock Polarity 0 SCLK idle low 1...

Page 238: ...0 9 8 Reserved 7 6 5 4 3 2 1 0 DIVIDER Table 5 92 SPI Clock Divider Register SPI0_CLKDIV address 0x4003_0004 Bits Description 31 8 Reserved Reserved 7 0 DIVIDER Clock Divider Register The value in thi...

Page 239: ...me out counter is Slave engine clock If the value is 0 it indicates the slave mode time out function is disabled 15 14 Reserved Reserved 13 SSINAIEN Slave Select Inactive Interrupt Enable 0 Slave sele...

Page 240: ...eceive is started and will be de asserted after each transmit receive is finished 2 SSACTPOL Slave Select Active Level This bit defines the active status of slave select signal SPI0_SS0 1 0 The slave...

Page 241: ...fect 1 Reset the PDMA control logic of the SPI controller This bit will be cleared to 0 automatically 1 RXPDMAEN Receive PDMA Enable Setting this bit to 1 will start the receive PDMA process The SPI c...

Page 242: ...11 4 word will transmit 27 26 Reserved Reserved 25 24 RXTH Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 els...

Page 243: ...interrupt Disabled 1 RX FIFO threshold interrupt Enabled 1 TXRST Clear Transmit FIFO Buffer 0 No effect 1 Clear transmit FIFO buffer The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set...

Page 244: ...ffer clear function of TXRST or RXRST Note Both the TXRST RXRST need 3 system clock 3 engine clocks the status of this bit allows the user to monitor whether the clear function is busy or done 22 20 R...

Page 245: ...n the receive FIFO buffer is larger than the setting value of RXTH Note If RXTHIEN 1 and RXTHIF 1 the SPI controller will generate a SPI interrupt request 9 RXFULL Receive FIFO Buffer Full Indicator R...

Page 246: ...t occur 1 Slave select active interrupt event has occur Note This bit will be cleared by writing 1 to itself 1 UNITIF Unit Transfer Interrupt Status 0 No transaction has been finished since this bit w...

Page 247: ...8 RXTSNCNT 7 6 5 4 3 2 1 0 RXTSNCNT Table 5 98 SPI Receive Transaction Count SPI0_RXTSNCNT address SPIx_BA 0x18 Bits Description 31 16 Reserved Reserved 16 0 RXTSNCNT DMA Receive Transaction Count Wh...

Page 248: ...12 11 10 9 8 TX 7 6 5 4 3 2 1 0 TX Table 5 99 SPI Data Transmit Register SPI0_TX address SPIx_BA 0x20 Bits Description 31 0 TX Data Transmit Register A write to the data transmit register pushes data...

Page 249: ...eive Register 0x0000_0000 31 30 29 28 27 26 25 24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Table 5 100 SPI Data Receive Register SPI0_RX address SPIx_BA 30 Bits Descri...

Page 250: ...oller can be set as a master also can be set as a slave controlled by an off chip master device 5 10 2 Features Supports master or slave mode operation Configurable word length of up to 32 bits Up to...

Page 251: ...p master device The SPI engine clock rate of slave device must be faster than the SPI serial clock rate of the master device The frequency of SPI engine clock cannot be faster than the APB clock rate...

Page 252: ...cording to registers SPI1_SSCTL SS In this mode SPI controller will assert SSB when transaction is triggered and de assert when data transfer is finished If the SPI1_SSCTL AUTOSS bit is cleared the sl...

Page 253: ..._SCLK Note that RXNEG should be the inverse of TXNEG for standard SPI operation 5 10 4 12Word Sleep Suspend The bit field SPI1_CTL SLEEP provides a configurable suspend interval of SLEEP 2 serial cloc...

Page 254: ...yte0 N A TX_BIT_LEN 24 bits TX_BIT_LEN 16 bits TX_BIT_LEN 32 bits MSB first MSB first MSB first Time N A N A Byte0 N A TX_BIT_LEN 8 bits MSB first N A N A Byte0 N A TX_BIT_LEN 8 bits MSB first BYTE_EN...

Page 255: ...Byte2 Byte1 0x20000010 0x20000014 unsigned char ucSPI_DATA 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 unsigned int uiSPI_DATA unsigned int ucSPI_DATA ucSPI_DATA uiSPI_DATA RAM Address RAM Contents 7 0 31...

Page 256: ...t data is written into this buffer again Before the FIFO bit is set the user can write first data into SPI1_TX buffer Setting FIFO active will load the first data into the current transmission buffer...

Page 257: ...only 00000000011111111111111110000111 SPICLK VARCLK CLK1 DIV CLK2 DIV2 Figure 5 62 Variable Serial Clock Frequency 5 10 5 SPI Timing Diagram In master slave mode the device address slave select SPI_SS...

Page 258: ...RXNEG 1 or 2 CTL CLKP 1 CTL TXNEG 1 CTL RXNEG 0 Rx0 1 Rx0 2 Rx0 3 Rx0 4 Rx0 5 Rx0 6 MSB Rx0 7 LSB Rx0 0 Figure 5 64 SPI Timing in Master Mode Alternate Phase of SPICLK SPICLK MOSI Slave Mode CTL SLVAE...

Page 259: ...1 CTL LSB 1 CTL TXNUM 0x01 CTL TXBITLEN 0x08 MISO Tx0 1 Tx0 7 Tx1 0 Tx1 6 MSB Tx1 7 LSB Tx0 0 CLKP 0 CLKP 1 SPI SS SS LVL 1 SS LVL 0 1 CTL CLKP 0 CTL TXNEG 0 CTL RXNEG 1 or 2 CTL CLKP 1 CT LTXNEG 1 C...

Page 260: ...so that data changes on falling edge of SCLK set SPI1_CTL RXNEG 0 so that data is latched into device on positive edge of SCLK set SPI1_CTL TXBITLEN 8 and SPI_CNTRL TXNUM 0 for a single byte transfer...

Page 261: ...TL TXBITLEN 8 and SPI1_CTL TXNUM 0 for a single byte transfer and finally set SPI1_CTL LSB 1 for LSB first transfer 10 If SPI slave is to transmit one byte of data to the off chip master device write...

Page 262: ...IV SPI1_BA 0x04 R W Clock Divider Register Master Only 0x0000_0000 SPI1_SSCTL SPI1_BA 0x08 R W Slave Select Register 0x0000_0000 SPI1_RX0 SPI1_BA 0x10 R Data Receive Register 0 0x0000_0000 SPI1_RX1 SP...

Page 263: ...nabled interface will automatically generate a SS signal for an entire PDMA access transaction 27 TXFULL Transmit FIFO FULL STATUS 1 The transmit data FIFO is full 0 The transmit data FIFO is not full...

Page 264: ...ween each byte transmitted 18 SLAVE Master Slave Mode Control 0 Master mode 1 Slave mode 17 IE Interrupt Enable 0 Disable SPI Interrupt 1 Enable SPI Interrupt to CPU 16 IF Interrupt Flag 0 Indicates t...

Page 265: ...irst on the line bit 0 of SPI1_TX0 1 and the first bit received from the line will be put in the LSB position in the Rx register bit 0 of SPI1_RX0 1 9 8 TXNUM Transmit Receive Word Numbers This field...

Page 266: ...01000 8 bit 01001 9 bit 01010 10 bit 01011 11 bit 01100 12 bit 01101 13 bit 01110 14 bit 01111 15 bit 10000 16 bit 10001 17 bit 10010 18 bit 10011 19 bit 10100 20 bit 10101 21 bit 10110 22 bit 10111...

Page 267: ...hen a transfer is in progress writing to any register of the SPI master slave core has no effect SPI Divider Register DIVIDER Register Offset R W Description Reset Value SPI1_CLKDIV SPI1_BA 0x04 R W C...

Page 268: ...r Offset R W Description Reset Value SPI1_SSCTL SPI1_BA 0x08 R W Slave Select Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6...

Page 269: ...e level of device slave select signal SPISSx0 1 0 The slave select signal SPISSx0 1 is active at low level falling edge 1 The slave select signal SPISSx0 1 is active at high level rising edge 1 Reserv...

Page 270: ...fset R W Description Reset Value SPI1_RX1 SPI1_BA 0x14 R Data Receive Register 1 0x0000_0000 31 30 29 28 27 26 25 24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Table 5 1...

Page 271: ...SPI1_CTL register For example if TXBITLEN is set to 0x08 and the TXNUM is set to 0x0 the bit SPI1_TX0 7 0 will be transmitted in next transfer If TXBITLEN is set to 0x00 and TXNUM is set to 0x1 the co...

Page 272: ...SPI1_BA 0x34 R W Variable Clock Pattern Register 0x007F_FF87 31 30 29 28 27 26 25 24 VARCLK 23 22 21 20 19 18 17 16 VARCLK 15 14 13 12 11 10 9 8 VARCLK 7 6 5 4 3 2 1 0 VARCLK Table 5 108 SPI Variable...

Page 273: ...Reserved 1 RXMDAEN Receive DMA Start 1 Enable 0 Disable Set this bit to 1 will start the receive DMA process SPI module will issue request to DMA module automatically 0 TXMDAEN Transmit DMA Start 1 En...

Page 274: ...period Period of timer clock input 8 bit prescale 1 24 bit CMPDAT Maximum count cycle time 1 TMR_CLK 2 8 2 24 Internal 24 bit up counter is readable through TIMERx_CNT Timer Data Register 5 11 3 Timer...

Page 275: ...oller 5 11 4 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value TMR Base Address TMRn_BA 0x4001_0000 0x20 n n 0 1 TMRn_CTL TMRn_BA 0x00 R W Timer...

Page 276: ...OPMODE 00b when the timer interrupt is generated INTEN 1b 29 INTEN Interrupt Enable Bit 0 Disable TIMER Interrupt 1 Enable TIMER Interrupt If timer interrupt is enabled the timer asserts its interrupt...

Page 277: ...e 24 17 Reserved Reserved 16 CNTDATEN Data Latch Enable When CNTDATEN is set TIMERx_CNT Timer Data Register will be updated continuously with the 24 bit up counter value as the timer is counting 1 Tim...

Page 278: ...0 Bits Description 31 25 Reserved Reserved 24 0 CMPDAT Timer Comparison Value CMPDAT is a 24 bit comparison register When the 24 bit up counter is enabled and its value is equal to CMPDAT value a Time...

Page 279: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TIF Table 5 112 Timer Interrupt Status Register TIMERx_INTSTS address 0x4001_...

Page 280: ...1 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT 23 16 15 14 13 12 11 10 9 8 CNT 15 8 7 6 5 4 3 2 1 0 CNT 7 0 Table 5 113 Timer Data Register TIMERx_CNT address 0x4001_000C x 0x20 Bits Desc...

Page 281: ...ires the watchdog timer will set Watchdog Timer Reset Flag RSTF high and reset CPU This reset will last 64 WDT clocks then CPU restarts executing program from reset vector 0x0000 0000 RSTF will not be...

Page 282: ...6 17 000 001 110 111 WDT_CLK Time out select Delay 1024 WDT clocks Watchdog Interrupt Watchdog Reset 1 WDT_CTL RSTCNT Reset WDT Counter Note 1 Watchdog timer resets CPU and lasts 64 WDT_CLK WDT_CTL WD...

Page 283: ...Date Sep 16 2019 283 Revision 2 4 5 12 1 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4000_4000 WDT_CTL WDT_BA 0x...

Page 284: ...r the Watchdog timer a watchdog reset will occur 1024 clock cycles later if WDG not reset The timeout is given by Interrupt Timeout 2 2xTOUTSEL 4 x WDT_CLK Reset Timeout 2 2xTOUTSEL 4 1024 x WDT_CLK W...

Page 285: ...Watchdog timer has no effect on this bit 0 Watchdog timer reset has not occurred 1 Watchdog timer reset has occurred NOTE This bit is cleared by writing 1 to this bit 1 RSTEN Watchdog Timer Reset Ena...

Page 286: ...enerator that is capable of dividing master clock input by divisors to produce the baud rate clock The baud rate equation is Baud Rate UART_CLK M BRD 2 where M and BRD are defined in Baud Rate Divider...

Page 287: ...g Table System Clock 49 152MHz Baud rate Mode0 err Mode1 err Mode2 err 921600 x A 4 B 8 1 2 A 51 0 6 460800 x A 10 B 8 1 2 A 104 0 3 230400 x A 22 B 8 A 7 B 11 1 2 1 2 A 211 0 2 115200 A 25 1 2 A 37 B...

Page 288: ...mit data payloads PDMA access support Auto flow control function CTS RTS supported Programmable baud rate generator Fully programmable serial interface characteristics o 5 6 7 or 8 bit character o Eve...

Page 289: ...as following UARTx_CLK HCLK CLK_APBCLK0 UARTx_EN 1 UARTDIV 1 CLK_CLKDIV0 UARTDIV Figure 5 71 UART Clock Control Diagram TX_FIFO TX shift register Control and Status registers Baud Rate Generator RX_F...

Page 290: ...ing the FIFO control registers UART_FIFO FIFO status registers UART_FIFOSTS and line control register UART_LINE for transmitter and receiver The time out control register UART_TOUT identifies the cond...

Page 291: ...put The IrDA SIR physical layer specifies use of Return to Zero Inverted RZI modulation scheme which represents logic 0 as an infrared light pulse The modulated output pulse stream is transmitted to a...

Page 292: ...vision 2 4 SOUT from uart TX IR_SOUT encoder output IR_SIN decorder input SIN To uart RX 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 0 1 0 0 1 1 Bit pulse width 3 16 bit width 3 16 bit width STOP BIT START BIT ST...

Page 293: ...LINEN bit to enable LIN Bus mode 2 Set UART_ALTCTL BRKFL to choose break field length The break field length is BRKFL 2 3 Fill 0x55 to UART_DAT to request synch field transmission 4 Request Identifier...

Page 294: ..._BA 0x0C R W UART Line Control Register 0x0000_0000 UARTn_MODEM UARTn_BA 0x10 R W UART Modem Control Register 0x0000_0000 UARTn_MODEMSTS UARTn_BA 0x14 R W UART Modem Status Register 0x0000_0010 UARTn_...

Page 295: ...fer FIFO Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Table 5 117 UART Receive FIFO Data Register UARTn_DAT...

Page 296: ...ta is available in receive FIFO 14 DMATXEN Transmit DMA Enable If enabled the UART will request DMA service when space is available in transmit FIFO 13 ATOCTSEN CTS Auto Flow Control Enable 0 Disable...

Page 297: ...Out Interrupt Enable 0 Mask off RXTOINT 1 Enable RXTOINT 3 MODEMIEN Modem Status Interrupt Enable 0 Mask off MODEMINT 1 Enable MODEMINT 2 RLSIEN Receive Line Status Interrupt Enable 0 Mask off RLSINT...

Page 298: ...flow Control Sets the FIFO trigger level when auto flow control will de assert RTS request to send Value Trigger Level Bytes 0 1 1 4 2 8 15 8 Reserved Reserved 7 4 RFITL Receive FIFO Interrupt RDAINT...

Page 299: ...hen RXRST is set all the bytes in the receive FIFO are cleared and receive internal state machine is reset 0 Writing 0 to this bit has no effect 1 Writing 1 to this bit will reset the receiving intern...

Page 300: ...is enabled If EPE 0 the parity bit is transmitted and checked as always set if EPE 1 the parity bit is transmitted and checked as always cleared 4 EPE Even Parity Enable 0 Odd number of logic 1 s are...

Page 301: ...5 121 UART Modem Control Register UARTn_MODEM address 0x4005_0010 Bits Description 31 14 Reserved Reserved 13 RTSSTS RTS Pin State Read Only This bit is the pin status of RTS 12 10 Reserved Reserved 9...

Page 302: ...CTSDETF Table 5 122 UART Modem Status Register UARTn_MODEMSTS address 0x4005_0014 Bits Description 31 9 Reserved Reserved 8 CTSACTLV Clear to send CTS Active Trigger Level This bit can change the CTS...

Page 303: ...ved Reserved 24 TXOVIF Tx Overflow Error Interrupt Flag If the Tx FIFO UART_DAT is full an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1 It will also genera...

Page 304: ...This bit is set to a logic 1 whenever the receive data input Rx is held in the space state logic 0 for longer than a full word transmission time that is the total time of start bit data bits parity s...

Page 305: ...terrupt Indicator to Interrupt Controller Logical AND of UART_INTEN DMARXEN or UART_INTEN DMATXEN and DLINIF 30 Reserved Reserved 29 DBERRINT DMA MODE Buffer Error Interrupt Indicator to Interrupt Con...

Page 306: ...nly This bit is set when the Rx receive data has a parity framing or break error at least one of UART_FIFOSTS BIF UART_FIFOSTS FEF and UART_FIFOSTS PEF is set If UART_INTEN RLSIEN is enabled the RLS i...

Page 307: ...equest will be generated NOTE This bit is read only and reset when bit UART_MODEMSTS CTSDETF is cleared by a write 1 2 RLSIF Receive Line Status Interrupt Flag Read Only This bit is set when the Rx re...

Page 308: ...terrupt MODEMINT MODEMIEN DMODEMI DMODEMIF CTSDETF Write 1 to CTSDETF Receive Line Status Interrupt RLSINT RLSIEN DRLSINT DRLSIF BIF or FEF or PEF Write 1 to BIF FEF PEF Table 5 126 UART Interrupt Sou...

Page 309: ...Reserved TOIC Table 5 127 UART Time Out Register UARTn_TOUT address 0x4005_0020 Bits Description 31 7 Reserved Reserved 6 0 TOIC Time Out Interrupt Comparator The time out counter resets and starts c...

Page 310: ...M0 EDIVM1 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 BRD 15 0 7 6 5 4 3 2 1 0 BRD 7 0 Table 5 128 UART Baud Rate Divider Register UARTn_BAUD address 0x4005_0024 Bits Description 31 30 Rese...

Page 311: ...Reserved LOOPBACK TXEN Reserved Table 5 129 UART IrDA Control Register UARTn_IRDA address 0x4005_0028 Bits Description 31 7 Reserved Reserved 6 RXINV Receive Inversion Enable 0 No inversion 1 Invert R...

Page 312: ...1 0 LINTXEN LINRXEN Reserved BRKFL Table 5 130 UART LIN Network Control Register UARTn_ALTCTL address 0x4005_002C Bits Description 31 8 Reserved Reserved 7 LINTXEN LIN TX Break Mode Enable 0 Disable L...

Page 313: ...26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved IRDAEN LINEN Table 5 131 UART Function Select Register UARTn_FUNCSEL address 0x4005_0030 Bits...

Page 314: ...ion with an external audio CODEC or DSP The peripheral is capable of mono or stereo audio transmission with 8 32bit word sizes Audio data is buffered in 8 word deep FIFO buffers and has DMA capability...

Page 315: ...K I2S0CKEN CLK_APBCLK0 29 I2S0SEL CLK_CLKSEL2 1 0 Figure 5 77 I2S Clock Control Diagram Transmit Contrl TXFIFO Receive Control RXFIFO Tx Shift Register Rx Shift Register I2S_CLK_GEN SLAVE_MODE MUX MUX...

Page 316: ...LK I2S_FS I2S_SDI I2S_SDO MSB Word N 1 Right Channel MSB LSB Word N Left Channel Word N Right Channel LSB Figure 5 79 I2S Bus Timing Diagram Format 0 I2S_BCLK I2S_FS I2S_SDI I2S_SDO MSB Word N 1 Right...

Page 317: ...eration N N 1 RIGHT LEFT 0 15 0 15 0 15 0 15 Mono 16 bit data mode Stereo 16 bit data mode N LEFT RIGHT N N 1 0 0 0 Mono 24 bit data mode Stereo 24 bit data mode 23 23 23 N LEFT RIGHT N N 1 0 31 31 31...

Page 318: ...2S Base Address I2S_BA 0x400A_0000 I2S_CTL I2S_BA 0x00 R W I2S Control Register 0x0000_0000 I2S_CLK I2S_BA 0x04 R W I2S Clock Divider Register 0x0000_0000 I2S_IEN I2S_BA 0x08 R W I2S Interrupt Enable...

Page 319: ...t DMA When TX DMA is enables I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full 0 Disable TX DMA 1 Enable TX DMA 19 RXCLR Clear Receive FIFO Write 1 to clear receive FIFO...

Page 320: ...If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set Threshold TXTH words remaining in transmit FIFO 8 SLAVE Slave Mode I2S can operate as a maste...

Page 321: ...Manual Release Date Sep 16 2019 321 Revision 2 4 2 RXEN Receive Enable 0 Disable data receive 1 Enable data receive 1 TXEN Transmit Enable 0 Disable data transmit 1 Enable data transmit 0 I2SEN Enabl...

Page 322: ...ple rate For sample rate Fs the desired bit clock frequency is FBCLK Fs x Word_width_in_bytes x 16 For example if Fs 16kHz and word width is 2 bytes 16bit then desired bit clock frequency is 512kHz Th...

Page 323: ...1 and right channel has zero cross event 0 Disable interrupt 1 Enable interrupt 10 TXTHIEN Transmit FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in tr...

Page 324: ...Manual Release Date Sep 16 2019 324 Revision 2 4 0 RXUDIEN Receive FIFO Underflow Interrupt Enable If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1 0 D...

Page 325: ...nsmit FIFO 27 24 RXCNT Receive FIFO Level Read Only RXCNT number of words in receive FIFO 23 LZCIF Left Channel Zero Cross Flag Write 1 to Clear or Clear LZCEN 0 No zero cross detected 1 Left channel...

Page 326: ...Only This is set when receive FIFO is empty 0 Not empty 1 Empty 11 RXFULL Receive FIFO Full Read Only This bit is set when receive FIFO is full 0 Not full 1 Full 10 RXTHIF Receive FIFO Threshold Flag...

Page 327: ...onding source s must be cleared 0 No transmit interrupt 1 Transmit interrupt occurred 1 RXIF I2S Receive Interrupt Read Only This indicates that there is an active receive interrupt source This could...

Page 328: ...XX 31 30 29 28 27 26 25 24 TX 23 22 21 20 19 18 17 16 TX 15 14 13 12 11 10 9 8 TX 7 6 5 4 3 2 1 0 TX Table 5 136 I2S Transmit FIFO Register I2S_TX address 0x400A_0010 Bits Description 31 0 TX Transmit...

Page 329: ...XXX 31 30 29 28 27 26 25 24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Table 5 137 I2S Receive FIFO Register I2S_RX address 0x400A_0014 Bits Description 31 0 RX Receive...

Page 330: ...ber of bytes to transfer Source and destination addresses can be fixed automatically increment by the transfer size update by an arbitrary value span mode or wrap around a circular buffer When PDMA op...

Page 331: ...number of bytes from a source address to a destination address Both source and destination address can be configured as a fixed address an incrementing address or a wrap around buffer address The gene...

Page 332: ...XX00 PDMA_CURSADDRn PDMAn_BA 0x14 R PDMA Current Source Address Register of Channel n 0xFFFF_FFFF PDMA_CURDADDRn PDMAn_BA 0x18 R PDMA Current Destination Address Register of Channel n 0xFFFF_FFFF PDMA...

Page 333: ...nable Start a PDMA Operation 0 Write no effect Read Idle Finished 1 Enable PDMA data read or write transfer Note When PDMA transfer completed this bit will be cleared automatically If a bus error occu...

Page 334: ...tically and PDMA will start another transfer Cycle continues until software sets PDMA_CTLn CHEN 0 When PDMA_CTLn CHEN is disabled the PDMA will complete the active transfer but the remaining data in t...

Page 335: ...Release Date Sep 16 2019 335 Revision 2 4 0 CHEN PDMA Channel Enable Setting this bit to 1 enables PDMA s operation If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into...

Page 336: ...sfer Source Address Register of Channel n 0x4000_0000 31 30 29 28 27 26 25 24 SADDR 23 22 21 20 19 18 17 16 SADDR 15 14 13 12 11 10 9 8 SADDR 7 6 5 4 3 2 1 0 SADDR Table 5 139 PDMA Source Address Regi...

Page 337: ...alue PDMA_DADDRn PDMAn_BA 0x08 R W PDMA Transfer Destination Address Register of Channel n 0x4000_0000 Table 5 140 PDMA Destination Address Register PDMAT_DADDRn address 0x5000_8008 n 0x100 Bits Descr...

Page 338: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT 15 8 7 6 5 4 3 2 1 0 CNT 7 0 Table 5 141 PDMA Transfer Byte Count Register PDMA_TXCNTn address 0x5000_800C n 0x100 Bits Descr...

Page 339: ...6 5 4 3 2 1 0 Reserved POINTER Table 5 142 PDMA Internal Buffer Point Register PDMA_INTPNTn address 0x5000_8010 n 0x100 Bits Description 31 4 Reserved Reserved 3 0 POINTER PDMA Internal Buffer Pointer...

Page 340: ...14 R PDMA Current Source Address Register of Channel n 0xFFFF_FFFF Table 5 143 PDMA Current Source Address Register PDMA_CURSADDRn address 0x5000_8014 n 0x100 Bits Description 31 0 ADDR PDMA Current S...

Page 341: ...MA Current Destination Address Register of Channel n 0xFFFF_FFFF Table 5 144 PDMA Current Destination Address Register PDMA_CURDADDRn address 0x5000_8018 n 0x100 Bits Description 31 0 ADDR PDMA Curren...

Page 342: ...x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Table 5 145 PDMA Current Byte Count Register PDMA_CURTXCNTn address 0x5000_80...

Page 343: ...g of PDMA_DSCTn_CTL WAINTSEL This can be interrupts when the transaction has finished and has wrapped around and or when the transaction is half way in progress This allows the efficient implementatio...

Page 344: ...complete or half complete are met They are cleared by writing one to the bits 0001 Current transfer finished flag PDMA_CURTXCNT 0 0100 Current transfer half complete flag PDMA_CURTXCNT PDMA_TXCNT 2 7...

Page 345: ...AN Table 5 148 PDMA Span Increment Register PDMA_SPANn address 0x5000_8034 n 0x100 Bits Description 31 8 Reserved Reserved 7 0 SPAN Span Increment Register This is a signed number in range 128 127 for...

Page 346: ...n 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 SPAN Table 5 149 PDMA Current Span Increment Register PDMA_CURSPANn addre...

Page 347: ...roller Channel 3 Clock Enable Control 1 Enable Channel 3 clock 0 Disable Channel 3 clock 10 CH2CKEN PDMA Controller Channel 2 Clock Enable Control 1 Enable Channel 2 clock 0 Disable Channel 2 clock 9...

Page 348: ...0 SPI0TXSEL SPI0RXSEL Table 5 151 PDMA Service Selection Control Register PDMA_SVCSEL0 address 0x5000_8F04 Bits Description 31 28 I2STXSEL PDMA I2S Transmit Selection This field defines which PDMA cha...

Page 349: ...ies Technical Reference Manual Release Date Sep 16 2019 349 Revision 2 4 3 0 SPI0RXSEL PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive PDMA so...

Page 350: ...1 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved SARADCRXSEL 15 14 13 12 11 10 9 8 SPI1TXSEL SPI1RXSEL 7 6 5 4 3 2 1 0 UART1XSEL UART1RXSEL Table 5 152 PDMA Service Selection Control R...

Page 351: ...H2INTSTS CH1INTSTS CH0INTSTS Table 5 153 PDMA Global Interrupt Status Register PDMA_GINTSTS address 0x5000_8F0C Bits Description 31 4 Reserved Reserved 3 CH3INTSTS Interrupt Pin Status of Channel 3 Re...

Page 352: ...he volume control shares a clock source with the BIQ filter so CLK_APBCLK0 BIQALCEN also the volume value will multiply BIQ result so BIQ_DLCOEFF must be set to operate volume control 5 16 2 Volume Co...

Page 353: ...rved DPWMZCEN SDADCZCEN DPWMVOLEN SDADCVOLE N Bits Description 31 4 Reserved Reserved 3 DPWMZCEN DPWM Audio Signal Volume Zero Crossing Enable 0 disable zero crossing update gain 1 enable Zero crossin...

Page 354: ...04 R W ADC Volume Control Value 0x0004_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 VALUE 15 14 13 12 11 10 9 8 VALUE 7 6 5 4 3 2 1 0 VALUE Bits Description 31 24 Reserved Reserved 23...

Page 355: ...AL VOLCTRL_BA 0x08 R W DPWM Volume Control Value 0x0004_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 VALUE 15 14 13 12 11 10 9 8 VALUE 7 6 5 4 3 2 1 0 VALUE Bits Description 31 24 Res...

Page 356: ...DATAF In addition there are two other partitions a 4K Byte Boot Loader ROM LDROM and Configuration ROM CONFIG Upon chip power on the Cortex M0 CPU fetches code from APROM or LDROM determined by a boo...

Page 357: ...ck diagram of flash memory controller is shown as following AHB Slave Interface ISP Controller ICP Writer Interface 0x0000_0000 0x0001_FFFF Flash Operation Control Power On Initialization Data Out Con...

Page 358: ...Size Start Address End Address APROM 128 KB 0x0000_0000 0x0001_FFFF 128KB DFBA 1 if DFEN 0 DATAF User Configurable DFBA 0x0001_FFFF 128KB LDROM 4 KB 0x0010_0000 0x0010_0FFF CONFIG 8B 0x0030_0000 0x00...

Page 359: ...FF A write operation can only change a 1 bit to a 0 bit If a subset of the page needs to be changed the entire 512B page must be copied to another page or into SRAM in advance as entire page must be e...

Page 360: ...cted will trigger the NMI interrupt to processor 0 Enable 1 Disable brown out detect after power on 22 8 Reserved Reserved for future use 7 CBS Configuration Boot Selection 0 Chip will boot from LDROM...

Page 361: ...7 6 5 4 3 2 1 0 DFBA Table 6 3 User Configuration Register 1 Config1 address 0x0030_0004 accessible through ISP only Config1 Address 0x0030_0004 Bits Description 31 20 Reserved Reserved It is mandato...

Page 362: ...CTL BS can be set to 1 and a software reset issued This will cause the chip to boot from LDROM An example flow diagram of the ISP sequence is shown in Figure 6 5 The FMC_ISPCTL register is a protected...

Page 363: ...ce and ISP Procedure The ISP command set is shown in Table 6 4 Three registers determine the action of a command FMC_ISPCMD is the command register and accepts commands for reading ID registers and re...

Page 364: ...0B x x x Returns 0x0000_00DA Read Device ID 0x0C x x 0x00000 FLASH Page Erase 0x22 0 A 20 A 19 0 x FLASH Program 0x21 0 A 20 A 19 0 Data input FLASH Read 0x00 0 A 20 A 19 0 Data output CONFIG Page Era...

Page 365: ...Base Address FMC_BA 0x5000_C000 FMC_ISPCTL FMC_BA 0x00 R W ISP Control Register 0x0002_0000 FMC_ISPADDR FMC_BA 0x04 R W ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA 0x08 R W ISP Data Register 0...

Page 366: ...TL address 0x5000_C000 Bits Description 31 22 Reserved Reserved 21 CACHEDIS Cache Disable When set to 1 caching of flash memory reads is disabled 18 8 Reserved Reserved 6 ISPFF ISP Fail Flag This bit...

Page 367: ...odify this bit to select which ROM next boot is to occur This bit also functions as MCU boot status flag which can be used to check where MCU booted from This bit is initialized after power on reset w...

Page 368: ...31 30 29 28 27 26 25 24 ISPADDR 23 22 21 20 19 18 17 16 ISPADDR 15 14 13 12 11 10 9 8 ISPADDR 7 6 5 4 3 2 1 0 ISPADDR Table 6 7 ISP Address Register FMC_ISPADDR address 0x5000_C004 Bits Description 31...

Page 369: ...0x08 R W ISP Data Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT 23 22 21 20 19 18 17 16 ISPDAT 15 14 13 12 11 10 9 8 ISPDAT 7 6 5 4 3 2 1 0 ISPDAT Table 6 8 ISP Data Register FMC_ISPDAT address...

Page 370: ...ISP Command Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CMD Table 6 9 ISP Data Register FMC_ISPCMD a...

Page 371: ...18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Table 6 10 ISP Trigger Control Register FMC_ISPTRG address 0x5000_C010 Bits Description 31 1 Reserved Reserved 0 ISPGO...

Page 372: ..._XXXX 31 30 29 28 27 26 25 24 DFBA 23 22 21 20 19 18 17 16 DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Table 6 11 Data Flash Base Address Register FMC_DFBA address 0x5000_C014 Bits Descriptio...

Page 373: ...to 6 144MHz while a configurable decimation filter allows oversampling ratios of 64 128 192 and 384 The decimation input is 6 144 MHz oversample rate The SINC filter and low pass filter can down samp...

Page 374: ...y an interrupt driven approach can be used to monitor the FIFO 7 1 4 1 SDADC Clock Generator 0 1 CLK12M SDADCSEL CLK_CLKSEL1 3 2 SDADCCKEN CLK_APBCLK1 28 MCLK 1 SDADCDIV 1 SDADCDIV CLK_CLKDIV0 23 16 H...

Page 375: ...MHz 24 32 2 16 4 64 1 8KHz 384 3 072MHz 8 64 6 256 2 048MHz 12 64 4 128 1 024MHz 24 64 2 32 4 64 512KHz 48 32 2 16 4 64 1 Table 7 2 Sample Rates for MCLK 12 288MHz Fs DSR SD_CLK CLKDIV SDADC_CTL DSRAT...

Page 376: ...m384_12 txt 38 4Hz 384 38 4 10 384Hz 16000 BSRATE 3 10th order 5 stage low_decm384_24 txt 76 8Hz 384 76 8 5 3072Hz 2000 BS_OSR 0 10th order 5 stage low_decm3072_120 txt 384Hz 3072 384 8 Table 7 4 Samp...

Page 377: ...028631 08ead 0 555977 7f6d9 0 035671 7f74f 0 033953 7f8ce 0 028109 7fe14 0 007509 105f2 1 020729 004b1 0 018282 004c5 0 018627 0053f 0 020485 00754 0 028631 08ead 0 555977 10000 1 000000 10000 1 0000...

Page 378: ...ncy and Set SDADC_CLKDIV Setup FIFO data width SDADC_CTL FIFOBITS Setup down ampling rate set SDADC_CTL RATESEL 0 then set SDADC_CTL DSRATE BIQ_CTL SDADCWNSR for expected DSR sampling rate refer to Ta...

Page 379: ...tion Reset Value SDADC Base Address SDADC_BA 0x400E_0000 SDADC_DAT SDADC_BA 0x00 R SD ADC FIFO Data Read Register 0xxxxx_xxxx SDADC_EN SDADC_BA 0x04 R W SD ADC Enable Register 0x0000_0000 SDADC_CLKDIV...

Page 380: ...Data Read Register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RESULT 15 8 7 6 5 4 3 2 1 0 RESULT 7 0 Bits Description 15 0 RESULT Delta Sigma A...

Page 381: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Reserved DINEDGE SDADCEN Bits Description 31 3 Reserved Reserved 2 Reserved Reserved 1 DINEDGE A...

Page 382: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CLKDIV 7 0 Bits Description 31 8 Reserved Reserved 7 0 CLKDIV SD_C...

Page 383: ...uld be 0 10 9 Reserved Reserved 8 DMICEN Digital MIC Enable 1 turn digital MIC function input from GPIO 0 keep SDADC function 7 FIFOTHIE FIFO Threshold Interrupt Enable 0 disable interrupt whenever FI...

Page 384: ...able SDADC FIFO BIST testing Internal use 30 8 Reserved Reserved 7 4 POINTER SDADC FIFO Pointer Read Only The FULL bit and POINTER 3 0 indicates the field that the valid data count within the SDADC FI...

Page 385: ...cription Reset Value SDADC_PDMACTL SDADC_BA 0x14 R W SD ADC PDMA Control Register 0x0000_0000 31 30 29 28 27 26 25 24 RESVERVED 23 22 21 20 19 18 17 16 RESVERVED 15 14 13 12 11 10 9 8 RESVERVED 7 6 5...

Page 386: ...ondition defined by CMPCOND the internal match counter will increase by 1 When the internal counter reaches the value to CMPMATCNT 1 the CMPF bit will be set 3 CMPF Compare Flag When the conversion re...

Page 387: ...ondition defined by CMPCOND the internal match counter will increase by 1 When the internal counter reaches the value to CMPMATCNT 1 the CMPF bit will be set 3 CMPF Compare Flag When the conversion re...

Page 388: ...PGADISCH PGAGAIN PGAIBLOOP PGAIBCTR PGAMODE 7 6 5 4 3 2 1 0 PGAMODE PGAMUTE PGAPU Reserved BIAS PD Bits Description 31 30 AUDIOPATHSEL Audio Path Selection Connect SDADC input to 00 PGA default 01 MIC...

Page 389: ...in default 0 PGA_GAIN PGA_HZMODE 0 PGA_HZMODE 1 0 0dB 6dB 1 6dB 12dB 12 PGA_IBLOOP Trim PGA current 1 default 11 9 PGA_IBCTR Trim PGA Current 0 default 8 6 PGA_MODE Each bit has respective function as...

Page 390: ...ent of the LDO is 10mA The IA can sense and amplify the output signal of the Wheatstone bridge and buffer it before it goes to a high resolution Sigma Delta ADC SDADC 7 2 2 Features Bandgap Low noise...

Page 391: ...hile BCHOPEN is low but the low frequency chopper will only function when BCHOPEN is set high The instrumentation amplifier also has two sets of choppers one set running at a high frequency and one ru...

Page 392: ...12 0x3f code 0x20 doesn t exist Step9 Ignore the next 64 output cycles for signal stable Step10 Capture 64 cycles of output data and average store them in an array Step11 decrease INSTRAMP 9 4 if INST...

Page 393: ...nd LDO Control Register BS_BANDGP_LDO Register Offset R W Description Reset Value BS_BANDGPLDO BS_BA 0x0 R W Bridge Sense Bandgap and LDO Control Register 0x0000_400e 31 30 29 28 27 26 25 24 CLKEN CLK...

Page 394: ...1010 4 5 15 Reserved Reserved 14 DIVEN BS LDO Voltage Divider Enable 1 enable 0 disable 13 DISCHRG BS LDO Discharge 1 enable 0 disable 12 LDOEN BS LDO Bridge Bias Enable 1 enable 0 disable 11 Reserve...

Page 395: ...bandgap 7 12 mV 1000 bandgap 8 12 mV 1001 bandgap 7 12 mV 1010 bandgap 6 12 mV 1011 bandgap 5 12 mV 1100 bandgap 4 12 mV 1101 bandgap 3 12 mV 1110 bandgap 2 12 mV 1111 bandgap 1 12 mV 3 BCHOPLFEN BS...

Page 396: ...lt state 1 invert system chopper switches 29 28 SCHOPF BS Instrumentation Amplifer System chopper frequency 00 40Hz 01 80Hz 10 20Hz 11 10Hz 27 26 CHOPF BS Instrumentation Amplifer chopper frequency se...

Page 397: ...0 disable system chopper 18 CHOPEN BS Instrumentation Amplifer chopper enable 1 enable choppers in the three opamps 0 disable choppers in the three opamps 17 12 OFFSETP BS Instrumentation Amplifer off...

Page 398: ...to 36dB in 0 5 dB step Programmable biquad filter to support multiple sample rates from 8 48kHz PDMA data channel for streaming of PCM audio data 7 3 3 Block Diagram Non overlap Gen VSSSPK VCCSPK Non...

Page 399: ...oth the pre selected and newly selected clock sources must be turned on and stable 7 3 4 3 Determining Sample Rate The sample rate at which the DPWM block consumes audio data is given by Fs DWPM_CLK Z...

Page 400: ...DPWMCKEN CLKSEL1 DPWMSEL Reset DPWM IP block IPRST1 DPWMRST IPRST1 BIQ_RST Enable BIQ clock source APBCLK0 BIQALCEN Enable BIQ on DPWM path BIQ_CTL PATHSEL BIQ_CTL BIQEN BIQ_CTL DPWMPUSR BIQ_CTL STAGE...

Page 401: ...ion Reset Value DPWM Base Address DPWM_BA 0x4007_0000 DPWM_CTL DPWM_BA 0x00 R W DPWM Control Register 0x0000_0000 DPWM_STS DPWM_BA 0x04 R DPWM DATA FIFO Status Register 0x0000_0002 DPWM_DMACTL DPWM_BA...

Page 402: ...ed 15 12 RXTH DPWM FIFO Threshold If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting the RXTHIF bit will set to 1 else the RXTHIF bit will be cleared to 0 11 RXTHIE...

Page 403: ...Reference Manual Release Date Sep 16 2019 403 Revision 2 4 1 0 FIFOWIDTH DPWM FIFO DATA WIDTH SELETION From PDMA 00 PDMA MSB 24bits PWDATA 31 8 01 PDMA 16 bits PWDATA 15 0 10 PDMA 8bits PWDATA 7 0 11...

Page 404: ...IFO BIST testing DPWM FIFO can be testing by Cortex M0 Internal use 30 8 Reserved Reserved 7 4 FIFOPTR DPWM FIFO Pointer Read Only The FULL bit and FIFOPOINTER indicates the field that the valid data...

Page 405: ...0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DMAEN Table 7 3 DPWM PDMA Control Register DPWM_DMACTL address 0x400...

Page 406: ...FIFO Input 0x0000_0000 31 30 29 28 27 26 25 24 INDATA 23 22 21 20 19 18 17 16 INDATA 15 14 13 12 11 10 9 8 INDATA 7 6 5 4 3 2 1 0 INDATA Table 7 4 DPWM FIFO Input DPWM_DATA address 0x4007_000C Bits D...

Page 407: ...0 9 8 Reserved 7 6 5 4 3 2 1 0 ZOHDIV Table 7 5 DPWM Zero Order Hold Division Register DPWM_ZOHDIV address 0x4007_0010 Bits Description 31 8 Reserved Reserved 7 0 ZOHDIV DPWM Zero Order Hold Down samp...

Page 408: ...nalog Multiplexer Programmable Gain Amplifier PGA for Audio Path HIRC Frequency Control CapSense Relaxation Oscillator Oscillator Frequency Measurement block 7 4 3 Register Map R read only W write onl...

Page 409: ...consists of a switchable resistive divider connected to the device VMID pin A 4 7 F capacitor should be placed on this pin and returned to analog ground VSSA as shown in Before using the SDADC PGA or...

Page 410: ...d off after 50ms to save power 1 The Low Resistance reference is disconnected from VMID Default power down and reset condition 0 PULLDOWN VMID Pulldown 0 Release VMID pin for reference operation 1 Pul...

Page 411: ..._LDOSEL ANA_BA 0x20 R W LDO Voltage Select Register 0x0000_0000 7 6 5 4 3 2 1 0 Reserved LDOSEL Table 7 7 LDO Voltage Control Register ANA_LDOSEL address 0x4008_0020 Bits Description 31 3 Reserved Res...

Page 412: ...ered to VD33 0 Enable LDO 1 Power Down 7 4 6 Microphone Bias Replaced by Bridge Sense ADC Microphone Bias Enable Register ANA_MICBEN Register Offset R W Description Reset Value ANA_MICBEN ANA_BA 0x2C...

Page 413: ...ency Measurement Block Diagram I2S_WS X032K Counter 16 bits PCLK EN FREQ_CNT 15 0 FM_DONE FM_SEL 1 0 XI32K OSC32K M U X OSC16K CYCLE_CNT 8 bits FM_CYCLE 7 0 Figure 7 8 Oscillator Frequency Measurement...

Page 414: ...nual Release Date Sep 16 2019 414 Revision 2 4 ANA_FQMMCTL FQMMEN TRUE while ANA_FQMMCTL MMSTS 1 Timeout 0x100000 if Timeout 0x100000 return E_DRVOSC_MEAS_TIMEOUT Freq ANA_FQMMCNT ANA_FQMMCTL FQMMEN F...

Page 415: ...im Register 0x0000_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 COARSE 7 6 5 4 3 2 1 0 OSCTRIM Table 7 11 Oscillator Trim Register ANA_TRIM address 0x40...

Page 416: ...er ANA_FQMMCTL address 0x4008_0094 Bits Description 31 FQMMEN FQMMEN 0 Disable Reset block 1 Start Frequency Measurement 30 24 Reserved Reserved 23 16 CYCLESEL Frequency Measurement Cycles Number of r...

Page 417: ...24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FQMMCNT 7 6 5 4 3 2 1 0 FQMMCNT Table 7 13 Frequency Measurement Count Register ANA_FQMMCNT address 0x4008_0098 Bits Description 31...

Page 418: ...QMMCYC 15 14 13 12 11 10 9 8 FQMMCYC 7 6 5 4 3 2 1 0 FQMMCYC Table 7 14 Frequency Measurement Cycle Register ANA_FQMMCYC address 0x4008_009C Bits Description 31 24 Reserved Reserved 23 0 FQMMCYC Frequ...

Page 419: ...by setting ALCEN The ALC shares a clock source with the Biquad filter so CLK_APBCLK0 BQALCKEN must be set to operate ALC The BIQ result also multiply the ALC result so BIQ should work together The AL...

Page 420: ...r of the ALC PGA Input PGA Output PGA Gain Figure 7 11 ALC Normal Mode Operation 7 5 1 2 ALC Hold Time Normal mode Only The hold parameter HOLDTIME configures the time between detection of the input s...

Page 421: ...loads the SDADC output value when the absolute value of the SDADC output exceeds the current measured peak otherwise the peak decays towards zero until a new peak has been identified This sequence is...

Page 422: ...at an input zero crossing Enabling zero crossing detection limits clicks and pops that may occur if the gain changes while the input signal has a high volume There are two zero crossing detection enab...

Page 423: ...ead and write Register Offset R W Description Reset Value ALC Base Address ALC_BA 0x400B_0090 ALC_CTL ALC_BA 0x00 R W ALC Control Register 0x0000_0000 ALC_GAIN ALC_BA 0x04 R W ALC GAIN Control Registe...

Page 424: ...12 11 10 9 8 TARGETLV 2 0 MODESEL DECAYSEL 7 6 5 4 3 2 1 0 ATKSEL NGEN NGTHBST Bits Description 31 PKLIMEN ALC Peak Limiter Enable Default is 0 Please set as 1 30 PKSEL ALC Gain Peak Detector Select...

Page 425: ...l 0 28 5 dB 1 27 dB 2 25 5 dB 3 24 dB 4 22 5 dB 5 21 dB 6 19 5 dB 7 18 dB 8 16 5 dB 9 15 dB 10 13 5 dB 11 12 dB 12 10 5 dB 13 9 dB 14 7 5 dB 15 6 dB 12 MODESEL ALC Mode 0 ALC normal operation mode 1 A...

Page 426: ...N Control Register ALC_GAIN address 0x400B_0094 31 30 29 28 27 26 25 24 PKLIMT 15 8 23 22 21 20 19 18 17 16 PKLIMIT 7 0 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 INITGAINEN ALCZCD INITGAIN Bits D...

Page 427: ...ual Release Date Sep 16 2019 427 Revision 2 4 5 0 INITGAIN ALC Initial Gain Set ALC initial gain Selects the PGA gain setting from 12dB to 35 25dB in 0 75dB step size 0x00 is lowest gain setting at 12...

Page 428: ...ALC GAIN Current ADC gain setting 19 11 PEAKVAL Peak Value 9 MSBs of measured absolute peak value 10 2 P2PVAL Peak to peak Value 9 MSBs of measured peak to peak value 1 NOISEF Noise Flag Asserted whe...

Page 429: ...Reserved Reserved 13 GMINIF GAIN less than minimum GAIN interrupt flag 12 GMAXIF GAIN more than maximum GAIN interrupt flag 11 GDECIF GAIN Decrease interrupt flag 10 GINCIF GAIN Increase interrupt fl...

Page 430: ...all the pins which will have capacitive sensing Set CYCCNT CYCLE_CNT for numbers of cycle to time a capacitive sensing Select scan mode by setting CTRL MODE0 1 Set CTRL MODE1 for interrupt with DUR_CN...

Page 431: ...on 01 from VH1 0 9 VDDA 10 from VM 0 5 VDDA 11 from VL1 0 1 VDDA A0PSEL Connect To SAR ADC8 no connection Figure 7 16 Operational Amplifier 0 Switch Control The following diagram and table illustrate...

Page 432: ...ADC9 OPA1 10k 560k A1O2N PGAEN PGAEN A0O2A1N A0O2A1P VH1 VM VL1 no connection Figure 7 17 Operational Amplifier 1 Switch Control The following diagram is OPAs bias setting If the OPBIASEN is set to 1...

Page 433: ...T INT select CINT0 C2OUTEN C1OUTEN C1OUT C2OUT Figure 7 19 Comparator Switch Control 7 6 6 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value CSC...

Page 434: ...when operation finished 27 24 DUR_CNT CSCAN Duration Count This counter is used to set a wakeup time after a capacitive sensing scan is complete It is in units of low frewquency clock period either LX...

Page 435: ...selects the channel GPIOB 15 0 to perform measurement on CSCAN Cycle Count Control Register CSCAN_CYCCNT Register Offset R W Description Reset Value CSCAN_CYCCNT CSCAN_BA 0x04 R W CSCAN Cycle Count C...

Page 436: ...CYCLE_CNT 4 might disrupt Capsense Interrupt and power mode wake up It is recommended to check result of CYCLE_CNT 2 4 cycles when SLOW_CLK 0 to avoid overflow the scan counter CSCAN Count Register CS...

Page 437: ...on Reset Value CSCAN_AGPIO CSCAN_BA 0x10 R W CSCAN Analog GPIO function Register 0x0000_0000 Table 7 23 CSCAN AGPIO Register CSCAN_AGPIO address 0x400D_0010 31 30 29 28 27 26 25 24 Reseverd 23 22 21 2...

Page 438: ...A1OEN A1EN 7 6 5 4 3 2 1 0 A0X A0O2N A0PSEL A0PS A0NS A0OEN A0EN Bits Description 31 25 Reserved Reserved 26 A1O2CIN OPA1 output to comparator input control bit 0 disable 1 enable 25 A0O2CIN OPA0 out...

Page 439: ...ntrol Bit 0 no connection 1 from A0P pin 10 A1NS A1N Pin to OPA1 Inverting Input Control Bit 0 no connection 1 from A0N pin 9 A1OEN OPA1 Output Enable or Disable Control Bit 0 disable 1 enable 8 A1EN...

Page 440: ...8 17 16 Reserved C2OUT C1OUT 15 14 13 12 11 10 9 8 CMPES Reserved Reserved C2INTEN C2OUTEN C2PSEL CMP2EN 7 6 5 4 3 2 1 0 CNPSEL Reserved Reserved CMP_INT C1INTEN C1OUTEN C1NSEL CMP1EN Bits Description...

Page 441: ...N Comparator 2 enable or disable control 0 disable 1 enable 7 CNPSEL Comparator non inverting input control 0 from OPA output 1 from CNP pin 6 5 Reserved Reserved 4 CMP_INT Comparator Interrupt Set by...

Page 442: ...Fs Sample Rate and 256 OSR Biquad is released from reset by setting BIQ_CTL DLCOEFF 1 After 32 clock cycles processor can setup other Biquad parameters or re program coefficients before enabling filt...

Page 443: ...Register Offset R W Description Reset Value BIQ Base Address BIQ_BA 0x400B_0000 BIQ_COEFF0 BIQ_BA 0x00 R W Coefficient b0 In H z Transfer Function 3 16 format 1st stage BIQ Coefficients 0x0000_0000 B...

Page 444: ...cient a2 In H z Transfer Function 3 16 format 4st stage BIQ Coefficients 0x0000_0000 BIQ_COEFF20 BIQ_BA 0x50 R W Coefficient b0 In H z Transfer Function 3 16 format 5nd stage BIQ Coefficients 0x0000_0...

Page 445: ...0x0000_0000 BIQ_COEFF8 BIQ_BA 0x020 R W Coefficient a1 In H z Transfer Function 3 16 format 2nd stage BIQ Coefficients 0x0000_0000 BIQ_COEFF9 BIQ_BA 0x024 R W Coefficient a2 In H z Transfer Function...

Page 446: ...IQ_BA 0x060 R W Coefficient a2 In H z Transfer Function 3 16 format 5nd stage BIQ Coefficients 0x0000_0000 BIQ_COEFF25 BIQ_BA 0x64 R W Coefficient b0 In H z Transfer Function 3 16 format 6rd stage BIQ...

Page 447: ...1 0 PRGCOEFF SDADCWNSR DLCOEFF PATHSEL HPFON BIQEN Bits Description 31 12 Reserved Reserved 28 16 SRDIV SR Divider 15 12 Reserved Reserved 11 STAGE BIQ Stage Number Control 0 6 stage 1 5 stage 10 8 D...

Page 448: ...t delay enough time before changing the coefficients or turn the BIQ on 2 PATHSEL AC Path Selection for BIQ 0 used in SDADC path 1 used in DPWM path 1 HPFON High Pass Filter On 0 disable high pass fil...

Page 449: ...29 28 27 26 25 24 RAMINITF Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BISTDONE BISTFAILED BISTEN Bits Description 31 RAMINITF Coefficient Ram In...

Page 450: ...e cycle on all specified channels following the sequence from the lowest numbered channel to the highest numbered channel Continuous scan mode A D converter continuously performs Single cycle scan mod...

Page 451: ...ster CMPx ADC0 ADC1 16 to 1 Analog MUX Sample and Hold Comparator PDMA request RSLT 11 0 ADC_INT STADC Analog Macro ADC clock and ADC start signal VREF ADC channel select APB Bus VALID OVERRUN ADF ADC...

Page 452: ...n and stable Figure 7 21 SARADC Clock Generator 7 8 3 2 Single Mode In single mode A D conversion is performed only once on the specified single channel The operations are as follows 1 A D conversion...

Page 453: ...lest number 2 When A D conversion for each enabled channel is completed the result is sequentially transferred to the A D data register corresponding to each channel 3 When the conversions of all the...

Page 454: ...CTL is set to 1 by software A D conversion starts on the channel with the smallest number 2 When A D conversion for each enabled channel is completed the result of each enabled channel is stored in th...

Page 455: ...e It is stopped only when external condition trigger condition disappears If edge trigger condition is selected the high and low state must be kept at least 4 PLCKs Pulse that is shorter than this spe...

Page 456: ...t STATUS ADCMPF0 CMP0 ADCMPIE STATUS ADCMPF1 CMP1 ADCMPIE SARADC_INT ADEF ADCIE Figure 7 26 A D Controller Interrupt 7 8 3 8 Peripheral DMA Request When A D conversion is finished the conversion resul...

Page 457: ...ta Register 6 0x0000_0000 SARADC_DAT7 SARADC_BA 0x1c R SAR ADC Data Register 7 0x0000_0000 SARADC_DAT8 SARADC_BA 0x20 R SAR ADC Data Register 8 0x0000_0000 SARADC_DAT9 SARADC_BA 0x24 R SAR ADC Data Re...

Page 458: ...x18 R SAR ADC Data Register 6 0x0000_0000 SARADC_DAT7 SARADC_BA 0x1c R SAR ADC Data Register 7 0x0000_0000 SARADC_DAT8 SARADC_BA 0x20 R SAR ADC Data Register 8 0x0000_0000 SARADC_DAT9 SARADC_BA 0x24 R...

Page 459: ...conversion result is gone It is cleared by hardware after DAT register is read 15 12 Reserved Reserved 11 0 RESULT A D Conversion Result This field contains conversion result of SARADC 12 bit SARADC c...

Page 460: ...verter is busy at conversion This bit is mirror of as SWTRG bit in CTL 2 ADCMPF1 Compare Flag When the selected channel A D conversion result meets setting condition in SARADC_CMP1 then this bit is se...

Page 461: ...Reserved 23 22 21 20 19 18 17 16 Reserved DATA 17 16 15 14 13 12 11 10 9 8 DATA 15 8 7 6 5 4 3 2 1 0 DATA 7 0 Bits Description 31 18 Reserved Reserved 17 0 DATA SAR ADC PDMA Current Transfer Data Regi...

Page 462: ...analog control register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Reserved 23 22 21 20 19 18 17 16 Reserved SAR_VREF Reserved Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SAR_SE...

Page 463: ...leared to 0 by hardware automatically at the ends of single mode and single cycle scan mode In continuous scan mode A D conversion is continuously performed until software writes 0 to this bit or chip...

Page 464: ...ternal STADC pin Others Reserved Software should disable TRGEN and SWTRG before change HWTRGSEL 3 2 OPMODE A D Converter Operation Mode 00 Single conversion 01 Reserved 10 Single cycle scan 11 Continu...

Page 465: ...0 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved Reserved Reserved 15 14 13 12 11 10 9 8 CHEN 15 8 7 6 5 4 3 2 1 0 CHEN 7 0 Bits Description 31 12 Reserved Reserved 23 20 Reserved R...

Page 466: ...ved 27 16 CMPDAT Comparison Data The 12 bit data is used to compare with conversion result of specified channel When ADCFMbit is set to 0 SARADC comparator compares CMPDAT with conversion result with...

Page 467: ...Reserved 1110 Reserved 1111 Reserved 2 CMPCOND Compare Condition 0 Set the compare condition as that when a 12 bit A D conversion result is less than the 12 bit CMPDAT CMPx 27 16 the internal match c...

Page 468: ...1 SPI0_MOSI0 11 10 9 8 41 15 0 1 uF 47 uF ISD91260 LQFP64 XI32K XO32K 31 30 20pF 20pF 32 768K 64 MICBIAS 4 7uF VMID 59 VREG 39 1uF 6 VDDB 5 VDDBS 1uF 0 1uF VSSSPK 22 DMIC_CLK DMIC_DAT 0 1uF VDD DMIC N...

Page 469: ...ISD91200 Series Technical Reference Manual Release Date Sep 16 2019 469 Revision 2 4 9 PACKAGE DIMENSIONS 9 1 64L LQFP 7x7x1 4mm footprint 2 0mm...

Page 470: ...ISD91200 Series Technical Reference Manual Release Date Sep 16 2019 470 Revision 2 4 9 2 QFN 32L 4X4 mm2 Thickness 0 8mm Max Pitch 0 40mm...

Page 471: ...INFORMATION I9 ISD Audio Product Family Product Series 1 Cortex M0 Flash ROM 0 12KB 3 64KB 6 128KB SRAM Feature Blank Standard C Voice Recognition P SARADC playback only G Basic feature set B Bridge S...

Page 472: ...Rename flash sector size as page size Power distruibution diagram revised OPA diagram revised V2 0 Oct 17 2017 Add figure number in SARADC change clock source naming formal release V2 1 Nov 13 2017 SP...

Page 473: ...ed to support or sustain life Furthermore Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation where personal injury death or seve...

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