ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 284 -
Revision 2.4
5.12.2 Register Description
Watchdog Timer Control Register (WDT_CTL)
This is a protected register, to write to register,
first issue the unlock sequence (
refer to SYS_REGLCTL
). Only
flag bits, IF and RSTF are unprotected and can be write-cleared at any time.
Register
Offset
R/W
Description
Reset Value
WDT_CTL
0x00
R/W
Watchdog Timer Control Register
0x0000_0700
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
TOUTSEL
7
6
5
4
3
2
1
0
WDTEN
INTEN
Reserved
IF
RSTF
RSTEN
RSTCNT
Bits
Description
[31:11]
Reserved
Reserved.
[10:8]
TOUTSEL
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset
will occur 1024 clock cycles later if WDG not reset. The timeout is given by:
Interrupt Timeout = 2^(2x4) x WDT_CLK.
Reset Timeout = (2^(2x4) +1024) x WDT_CLK.
Where WDT_CLK is the period of the Watchdog Timer clock source.
[7]
WDTEN
Watchdog Timer Enable
0 = Disable the Watchdog timer (This action will reset the internal counter).
1 = Enable the Watchdog timer.
[6]
INTEN
Watchdog Timer Interrupt Enable
0 = Disable the Watchdog timer interrupt.
1 = Enable the Watchdog timer interrupt.
[5:4]
Reserved
Reserved.
[3]
IF
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to
indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer
interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
0 = Watchdog timer interrupt has not occurred.
1 = Watchdog timer interrupt has occurred.
NOTE: This bit is cleared by writing 1 to this bit.
