ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 234 -
Revision 2.4
5.9.7
Register Map
R
: read only,
W
: write only,
R/W
: both read and write
Register
Offset
R/W
Description
Reset Value
SPI Base Address:
SPI0_BA = 0x4003_0000
SPI0_CTL
S 0x00
R/W
Control and Status Register
0x0000_0034
SPI0_CLKDIV
S 0x04
R/W
Clock Divider Register (Master Only)
0x0000_0000
SPI0_SSCTL
S 0x08
R/W
Slave Select Register
0x0000_0000
SPI0_PDMACTL
S 0x0C
R/W
SPI PDMA Control Register
0x0000_0000
SPI0_FIFOCTL
S 0x10
R/W
FIFO Control/Status Register
0x4400_0000
SPI0_STATUS
S 0x14
R/W
Status Register
0x0005_0110
SPI0_RXTSNCNT
S 0x18
R/W
Receive Transaction Count Register
0x0000_0000
SPI0_TX
S 0x20
W
FIFO Data Transmit Register
0x0000_0000
SPI0_RX
S 0x30
R
FIFO Data Receive Register
0x0000_0000
SPI0_VERNUM
S 0x50
R
IP Version Number Register
0x0201_0001