ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
transmission will start when the slave device receives clock signal from master. Data can be written to
SPI0_TX register as long as the TXFULL flag is 0. After all data have been drawn out by the SPI
transmission logic unit and the SPI0_TX register is not updated by software, the TXEMPTY flag will be
set to 1.
If there is no any data is written to the SPI0_TX register, the under-run event, TXUFIF
(SPI0_STATUS[19]) will active when the slave select active and the serial clock input this controller.
Under the previous condition, the Slave mode error 1, SLVURIF, SPI0_STATUS[7], will be set to 1
when SS goes to inactive state and transmit under-run occurs.
In Slave mode, during receiving operation, the serial data is received from SPI0_MOSI0/1 pin and
stored to SPI0_RX register. The reception mechanism is similar to Master mode reception operation. If
the receive FIFO buffer contains 8 unread data, the RXFULL flag will be set to 1 and the RXOVIF will
be set 1 if there is more serial data is received from SPIMOSI and follow-up data will be dropped. If the
receive bit counter mismatch with the DWIDTH when the slave select line goes to inactive state, the
Slave mode error 0, SLVBEIF, SPI0_STATUS[6], will be set to 1.
When the Slave select is active and the value of SLVTOCNT is not 0, the Slave time-out counter in the
SPI controller logic will start after the serial clock input. This counter will be clear after one transaction
done or the SLVTOCNT is set to 0. If the value of the time-out counter greater or equal than the value
of SLVTOCNT before one transaction done, the slave time-out event occurs abd the SLVTOIF,
SPI0_STATUS[5], will be set to 1.
A receive time-out function is built-in in this controller. When the receive FIFO is not empty and no read
operation in receive FIFO over 64 SPI clock period in Master mode or over 576 SPI engine clock period
in Slave mode, the receive time-out occurs and the SLVTOIF be set to 1. When the receive FIFO is
read by user, the time-out status will be cleared automatically.
5.9.4.18
DMA Receive Mode
The SPI controller supports DMA access to the transmit and receive FIFOs. When the DMA transmit
interface is active, DMA sub-system fills the TX FIFO to trigger SPI interface. When only DMA receive
function is required, an additional mode is provided to inform the SPI system of the number of transfers
desired so that SPI system can read ahead of DMA requests. When SPI0_CTL. RXTCNTEN is set, the
register SPI0_RXTSNCNT holds the number of SPI transactions (total number of bytes is determined
by SPI0_CTL.DWIDTH value).
5.9.5
SPI Timing Diagram
In master/slave mode, the device address/slave select (SPI0_SSB0/1) signal can be configured as
active low or active high by the SPI0_SSCTL.SSACTPOL bit.
The serial clock phase and polarity is controlled by CLKPOL, RXNEG and TXNEG bits. The bit length
of a transfer word is configured by the DWIDTH parameter. Whether data transmission is MSB first or
LSB first is controlled by the SPI0_CTL.LSB bit. Four examples of SPI timing diagrams for master/slave
operations and the related settings are shown as below.
