ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 154 -
Revision 2.4
Figure 5-15 Acknowledge on the I2C bus
5.6.2
Modes of Operation
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC call.
In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C port
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, and if the slave is willing to receive or transmit data from/to master(by setting the AA bit), an
acknowledge pulse will be transmitted out on the 9th clock. An interrupt is requested on both master
and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus master,
the hardware waits until the bus is free before the master mode is entered so that a possible slave
action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the slave
mode immediately and can detect its own slave address in the same serial transfer.
5.6.2.1
Master Transmitter Mode
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains
the slave address of the receiving device (7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic 0, and it is represented by “W” in the flow diagrams. Thus the first byte
transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an
acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
5.6.2.2
Master Receiver Mode
In this case the data direction bit (R/W) will be logic 1, and it is represented by “R” in the flow diagrams.
Thus the first byte transmitted is SLA+R. Serial data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are output to indicate the beginning and end of a serial
transfer.
5.6.2.3
Slave Receiver Mode
Serial data and the serial clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by hardware after reception of the slave address
and direction bit.
5.6.2.4
Slave Transmitter Mode
The first byte is received and handled as in the slave receiver mode. However, in this mode, the
direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while
the serial clock is input through SCL. START and STOP conditions are recognized as the beginning
and end of a serial transfer.
1
2
8
9
SCL FROM
MASTER
DATA OUTPUT BY
TRANSMITTER
DATA OUTPUT BY
RECEIVER
S
START
condition
clock pulse for
acknowledgement
not acknowledge
acknowledge
