ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.3.4.4
Level3: Deep Sleep mode.
The Deep Sleep mode is the lowest power state where the Cortex-M0 and all logic state are
preserved. In Deep Sleep mode the HIRC oscillator is shut down and a low speed oscillator is
selected, if LXT is active this source is selected, if not then LIRC is enabled and selected. All clocks to
the Cortex-M0 core are gated eliminating dynamic power in the core. Clocks to peripheral are gated
according to the CLK_SLEEPCTL
register, note however that HCLK is operating at a low frequency
and HIRC is not available. Deep Sleep mode is entered by setting System Control register bit 2:
SYSINFO_SCR |= (1UL << 2) and executing a WFI/WFE instruction. Software can determine whether
the device woke up from Deep Sleep by interrogating the register bit CLK_PWRSTSF.DSF.
5.3.4.5
Level4: Sleep mode.
The Sleep mode gates all clocks to the Cortex-M0 eliminating dynamic power in the core. In addition,
clocks to peripherals are gated according to the CLK_SLEEPCTL register. The mode is entered by
executing a WFI/WFE instruction and is released when an event occurs. Peripheral functions,
including PDMA can be continued while in Sleep mode. Using this mode power consumption can be
minimized while waiting for events such as a PDMA operation collecting data from the ADC, once
PDMA has finished the core can be woken up to process the data
5.3.5
Register Map
R:
read only,
W:
write only,
R/W:
both read and write
Register
Offset
R/W
Description
Reset Value
CLK Base Address:
CLK_BA = 0x5000_0200
CLK_PWRCTL
0x00
R/W
System Power Control Register
0xXX00_000D
CLK_AHBCLK
0x04
R/W
AHB Device Clock Enable Control Register
0x0000_0005
CLK_APBCLK0
0x08
R/W
APB Device Clock Enable Control Register
0x0000_0001
CLK_DPDSTATE
0x0C
R/W
Deep Power Down State Register
0x0000_XX00
CLK_CLKSEL0
0x10
R/W
Clock Source Select Control Register 0
0x0000_0038
CLK_CLKSEL1
0x14
R/W
Clock Source Select Control Register 1
0xF000_7703
CLK_CLKDIV0
0x18
R/W
Clock Divider Number Register
0x0000_1010
CLK_CLKSEL2
0x1C
R/W
Clock Source Select Control Register 2
0x0000_0000
CLK_SLEEPCTL
0x20
R/W
Sleep Clock Source Select Register
0xFFFF_FFFF
CLK_PWRSTSF
0x24
R/W
Power State Flag Register
0x0000_0000
CLK_DBGPD
0x28
R/W
Debug Port Power Down Disable Register
0x0000_00XX
CLK_WAKE10K
0x2C
R/W
Deep Power Down 10K Wakeup Timer
0x0000_0001
Note: In BSP register structure, the prefix is structure name, and register be no prefix, for example
CLK_ is the prefix, CLK_WAKE10K will be CLK->WAKE10K
