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6.18.4 Basic Configuration
The USBH clock source is derived from PLL. User has to set the PLL related configurations
before USB host controller is enabled. Set the USBHCKEN (CLK_AHBCLK[4]) bit to enable
USBH clock and 4-bit pre-scaler USBDIV (CLK_CLKDIV0[7:4]) to generate the proper USBH
clock rate. The proper USBH clock rate is 48 MHz.
6.18.5 Functional Description
AHB Interface
6.18.5.1
The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires
both master and slave bus operations. As a master, the Host Controller is responsible for running
cycles on the AHB bus to access EDs and TDs as well as transferring data between memory and
the local data buffer. As a slave, the Host Controller monitors the cycles on the AHB bus and
determines when to respond to these cycles. Configuration and non-real-time control access to
the Host Controller operational registers are through the AHB bus slave interface.
Host Controller
6.18.5.2
The host controller includes 5 functional blocks, including List Processing, Frame Management,
Interrupt Processing, Host Controller Bus Master and Data Buffer.
The List Processor manages the data structures from the Host Controller Driver and coordinates
all activity within the Host Controller.
The Frame Management is responsible for managing the frame specific tasks required by the
USB specification and the OpenHCI specification. These tasks are:
1) Management of the OpenHCI frame specific Operational Registers
2) Operation of the Largest Data Packet Counter.
3) Performing frame qualifications on USB Transaction requests to the SIE.
4) Generate SOF token requests to the SIE.
Interrupts are the communication method for HC-initiated communication with the Host Controller
Driver. There are several events that may trigger an interrupt from the Host Controller. Each
specific event sets a specific bit in the HcInterruptStatus register.
The Host Controller Bus Master is the central block in the data path. The Host Controller Bus
Master coordinates all access to the AHB Interface. There are two sources of bus mastering
within Host Controller: the List Processor and the Data Buffer Engine.
The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a
combination of a 64-byte latched based bi-directional asynchronous FIFO and a single DWORD
AHB Holding Register.
USB Interface
6.18.5.3
The USB interface includes the integrated Root Hub with an USB port, Port 1 as well as the Serial
Interface Engine (SIE) and USB clock generator. The interface combines responsibility for
executing bus transactions requested by the HC as well as the hub and port management
specified by USB.
The SIE is responsible for managing all transactions to the USB. It controls the bus protocol,
packet generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and
NRZI encoding. All transactions on the USB are requested from the List Processor and Frame
Manager.