M451
May. 4, 2018
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Rev.2.08
M4
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Watchdog Timer (WDT)
6.10
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (2
4
~ 2
18
) and the time-out interval is 1.6 ms ~ 26.214s if
WDT_CLK =
10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026
、
130
、
18 or 3 WDT_CLK reset
delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in
Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as
LIRC or
LXT.
6.10.3 Block Diagram
18- bit WDT Counter
0
…
... 15
..
4
16 17
000
001
110
111
:
:
WDT_ CLK
Time-
Out
Interval
Period
select
Reset
Delay
Period
Select
Watchdog
Interrupt
Watchdog
Reset
RSTCNT(WDT_CTL[0])
Reset WDT
Counter
WDTEN
(WDT_CTL[7])
Wakeup CPU from
Power - down mode
TOUTSEL
(WDT_CTL[10:8])
IF
(WDT_CTL[3])
INTEN
(WDT_CTL[6])
RSTEN
(WDT_CTL[1])
RSTF
(WDT_CTL[2])
WKEN
(WDT_CTL[4])
WKF
(WDT_CTL[5])
Figure 6.10-1 Watchdog Timer Block Diagram
Note1:
WDT resets CPU and lasts 63 WDT_CLK.
Note2:
The WDT reset delay period can be selected as 3/18/130/1026 WDT_CLK.
6.10.4 Clock Control
The WDT clock control are shown as follows.
