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M451
May. 4, 2018
Page
418
of
1006
Rev.2.08
M4
51
S
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RI
E
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CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
101
010
001
PCLK1
000
011
100
Legend:
HIRC = High Speed Internal clock signal
HXT = High Speed External clock signal
LIRC = Low Speed Internal clock signal
22.1184 MHz (HIRC)
10 kHz (LIRC)
4~24 MHz (HXT)
32.768 KHz (LXT)
TMR3_CLK
LXT = Low Speed External clock signal
T2~T3
TMR2CKEN(CLK_APBCLK0[4])
TMR3CKEN(CLK_APBCLK0[5])
TMR2SEL(CLK_CLKSEL1[18:16])
TMR3SEL(CLK_CLKSEL1[22:20])
101
010
001
PCLK0
000
011
100
22.1184 MHz (HIRC)
10 kHz (LIRC)
4~24 MHz (HXT)
32.768 KHz (LXT)
TMR1_CLK
T0~T1
TMR0CKEN(CLK_APBCLK0[2])
TMR1CKEN(CLK_APBCLK0[3])
TMR0SEL(CLK_CLKSEL1[10:8])
TMR1SEL(CLK_CLKSEL1[14:12])
TMR0_CLK
TMR2_CLK
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.8-2 Clock Source of Timer Controller
6.8.4 Basic Configuration
The peripheral clock source of Tiimer0 ~ Timer3 can be enabled in TMRxCKEN
(CLK_APBCLK0[5:2]) and selected as different frequency in TMR0SEL (CLK_CLKSEL1[10:8]) for
Timer0, TMR1SEL (CLK_CLKSEL1[14:12]) for Timer1, TMR2SEL (CLK_CLKSEL1[18:16]) for
Timer2 and TMR3SEL (CLK_CLKSEL1[22:20]) for Timer3.
6.8.5 Functional Description
Timer Interrupt Flag
6.8.5.1
Timer controller supports two interrupt flags; one is TIF (TIMERx_INTSTS[0]) and its set while
timer counter value CNT (TIMERx_CNT[23:0]) matches the timer compared value CMPDAT
(TIMERx_CMP[23:0]), the other is CAPIF (TIMERx_EINTSTS[0]) and its set when the transition
on the Tx_EXT pin associated CAPEDGE (TIMERx_EXTCTL[2:1]) setting.
Timer Counting Mode
6.8.5.2
Timer controller provides four timer counting modes: one-shot, periodic, toggle-output and
continuous counting operation modes:
One
–shot Mode
6.8.5.3
If timer controller is configured at one-shot mode (TIMERx_CTL[28:27] is 00) and CNTEN