NR Electric PCS-9611, Instruction Manual

Page: 69 / 300

3 Operation Theory
PCS-9611 Feeder Relay
3-33
Date: 2014-04-08
The two stages have same protection logics if they are set with definite time characteristics.
The logic diagram for the stage 1 negative sequence overcurrent protection is shown as below.
The negative sequence overcurrent block is a level detector that detects whether the negative
sequence current magnitude is above the threshold.
I
2
> [50/51Q1.I2_Set]
[50/51Q1.Blk]
[50/51Q1.En]
[50/51Q1.Op]
[50/51Q1.St]
[50/51Q1.En1]
&
t
NOC1
0
Figure 3.7-1 Logical diagram of the stage 1 NOC protection
Where:
[50/51Q1.I2_Set] is the current setting of the stage 1 negative sequence overcurrent
protection;
“t
NOC1
” is the setting [50/51Q1.t_Op], the time setting of the stage 1 negative sequence
overcurrent protection;
[50/51Q1.En] is the logic setting of the stage 1 negative sequence overcurrent protection;
[50/51Q1.En1] is the binary signal for enabling the NOC1 protection;
[50/51Q1.Blk] is the binary signal for blocking the NOC1 protection.
3.7.2 IDMT Negative Sequence Overcurrent Protection
The stage 2 negative sequence overcurrent protection also can be set with inverse definite
minimum time (IDMT) characteristic. It has the same inverse time characteristic with the IDMT
overcurrent protection (see Section 3.3.2 ), and the setting [50/51Q2.Opt_Curve] can be used to
select the expected curve.
The logic diagram of the negative sequence overcurrent protection is shown as below. The
negative sequence current block is a level detector that detects whether the current magnitude is
above the threshold.
I
2
> [50/51Q2.I2_Set]
[50/51Q2.Blk]
[50/51Q2.En]
[50/51Q2.Op]
[50/51Q2.St]
[50/51Q2.En1]
&
IDMT
[50/51Q2.Opt_Curve] = 0
Figure 3.7-2 Logic diagram of the IDMT negative sequence overcurrent protection
Where:
[50/51Q2.I2_Set] is the current setting of the stage 2 negative sequence overcurrent
protection;
[50/51Q2.En] is the logic setting of the stage 2 negative sequence overcurrent pro tection;