NR Electric PCS-9611, Instruction Manual

Page: 56 / 300

3 Operation Theory
PCS-9611 Feeder Relay
3-20
Date: 2014-04-08
[50/51G2.En]
[50/51G2.En1]
&
[50/51G2.Op]
&
50/51G2.HmBlk
50/51G2.Dir
I
0
> [50/51G2.3I0_Set]
[50/51G2.Blk]
[50/51G2.St]
t
ROC2
0
[50/51G5.En]
[50/51G5.En1]
&
[50/51G5.Op]
I
0
> [50/51G5.3I0_Set]
[50/51G5.Blk]
[50/51G5.St]
t
ROC5
0
[50/51G6.En]
[50/51G6.En1]
&
[50/51G6.Op]
I
0
> [50/51G6.3I0_Set]
[50/51G6.Blk]
[50/51G6.St]
t
ROC6
0
[50/51G3.En]
[50/51G3.En1]
[50/51G3.Opt_Curve] = 0
&
50/51G3.HmBlk
50/51G3.Dir
&
[50/51G3.Op]
I
0
> [50/51G3.3I0_Set]
[50/51G3.Blk]
[50/51G3.St]
t
ROC3
0
[50/51G4.En]
[50/51G4.En1]
[50/51G4.Opt_Curve] = 0
&
50/51G4.HmBlk
50/51G4.Dir
&
[50/51G4.Op]
I
0
> [50/51G4.3I0_Set]
[50/51G4.Blk]
[50/51G4.St]
t
ROC4
0
[50/51G1.En]
[50/51G1.En1]
&
[50/51G1.Op]
&
50/51G1.HmBlk
50/51G1.Dir
I
0
> [50/51G1.3I0_Set]
[50/51G1.Blk]
[50/51G1.St]
t
ROC1
0
Figure 3.5-1 Logic diagram of the No.1 zero sequence overcurrent protection
Where:
[50/51Gx.3I0_Set] (x: 1~6) is the current setting of the stage x (x: 1~6) zero sequence
overcurrent protection;
“t
ROCx
” (x: 1~6) is the setting [50/51Gx.t_Op] (x: 1~6), the time setting of the stage x (x: 1~6)
zero sequence overcurrent protection;
[50/51Gx.En] (x: 1~6) is the logic setting of the stage x (x: 1~6) zero sequence overcurrent
protection;
[50/51Gx.En1] (x: 1~6) is the binary signal for enabling the stage x (x: 1~6) zero sequence
overcurrent protection;
[50/51Gx.Blk] (x: 1~6) is the binary signal for blocking the stage x (x: 1~6) zero sequence
overcurrent protection;
[50/51Gx.Opt_Curve] (x: 3~4) is the setting for selecting the inverse time characteristic curve;