RM-384
System Module and User Interface
Page 5-24 Company Confidential Issue1
Copyright © 2009 Nokia. All rights reserved.
Clock distribution
The MSM6800A device derives all of its internal clock sources from three clock inputs: TCXO, SLEEP_XTAL, and
48XTAL. .
The TCXO clock input supports 19.2 MHz. An integrated PLL and M/N counter is used to create the required clock
sources when the TCXO frequency is 19.2 MHz.
The SLEEP_XTAL can support a 32.768 kHz clock source to drive the sleep controller during periods when most of
the MSM6800A device is powered down and the TCXO is disabled.
A 48 MHz crystal oscillator is used to generate the clock source for the USB interface and is not required for any
other subsystem of the MSM6800A device.
It is recommended that the USB clock source be shut down when the USB interface is not being used.
Subsystem clock regimes for MSM6800A
The MSM6800A clock tree basically has seven main sources:
PLL0: GPLL VCO = 196.608 MHz
PLL1: GPLL VCO = 172.8 MHz or 201.6 MHz (depending on ADSP operation)
PLL2: DCPLL VCO = 172.8 MHz
PLL3: DCPLL VCO = 268.8 MHz
.multimedia
oscillator = 24 MHz
Sleep oscillator = 32 .768 KHz
TCXO oscillator = 19.2 MHz
NOTE
The PLLs are all derived from the main TCXO input. All seven clocks are used throughout the MSM in
generating internal and interface clocks
TCXO Clock 19.2MHz
The MSM6800A device integrates a phase-locked loop (PLL) and an M/N counter to derive CHIPX16 and CHIPX8
from the TCXO clock input.
The TCXO clock input supports 19.2 MHz. An integrated PLL and M/N counter is used to create the required clock
sources when the TCXO frequency is 19.2 MHz.
