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Revision 1.0
211
Format:
sll rd, rt, sa
Description:
The contents of general register
rt
are shifted left by
sa
bits, inserting zeros into the low-order bits.
The result is placed in register
rd.
Operation:
Exceptions:
None
SLL
Shift Left Logical
31
25
26
20
21
15
16
SPECIAL
rt
6
5
5
rd
sa
SLL
5
5
6
11 10
6
5
0
0 0 0 0 0 0
0 0 0 0 0 0
SLL
0
0 0 0 0 0
T:
GPR[rd]
GPR[rt]
31– sa...0
|| 0
sa
Summary of Contents for Ultra64
Page 2: ...2 ...
Page 10: ...10 ...
Page 12: ...12 Figure 6 2 buildtask Operation 137 ...
Page 14: ...14 ...
Page 80: ...80 Vector Unit Instructions vmadm dres_int dres_int vconst 3 vmadn dres_frac vconst vconst 0 ...
Page 104: ...104 RSP Coprocessor 0 ...
Page 150: ...150 Advanced Information ...
Page 155: ...Revision 1 0 155 ...
Page 248: ...248 Exceptions None ...
Page 251: ...Revision 1 0 251 Exceptions None ...
Page 254: ...254 Exceptions None ...
Page 257: ...Revision 1 0 257 Exceptions None ...
Page 293: ...Revision 1 0 293 Exceptions None ...
Page 316: ...316 Exceptions None ...