Common FlexRIO with Integrated I/O Examples
In addition to the examples within the FlexRIO with Integrated IO Project Creator, NI
provides several examples that apply to all FlexRIO with Integrated I/O modules to help you
perform common tasks.
The following examples can be found in the NI Example Finder:
•
Show All FlexRIO with Integrated IO Hardware.vi
queries and displays a
set of hardware properties from all FlexRIO with Integrated I/O devices in a chassis.
•
Vivado Export Getting Started Ultrascale.lvproj
demonstrates the use
of the Vivado Project Export feature.
•
Read-Write Calibration Data.vi
demonstrates how to read and write calibration
data and metadata into the storage space of FlexRIO with Integrated I/O devices.
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The PXIe-1486 ships with socketed CLIP items that add module I/O to the LabVIEW project.
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PXIe-1486 Getting Started Guide
