Copyright © 2018 NEXCOM International Co., Ltd. All Rights Reserved.
35
EBC 355A User Manual
Chapter 3: BIOS Setup
CPU Configuration
This section is used to configure the CPU.
Exit
Advanced
Chipset
PCIPnP
Security
Main
Version 2.16.1243. Copyright (C) 2013 American Megatrends, Inc.
Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
→←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Disabled for Windows XP
CPU Configuration
Intel(R) Celeron(R) CPU J1900 @ 1.99GHz
CPU Signature
30678
Microcode Patch
815
Max
CPU Speed
1990 MHz
Min CPU Speed
1334 MHz
Processor Cores
4
Intel HT Technology
not Supported
Intel VT-x Technology
Supported
L1 Data Cache
24 kB x 4
L1 Code Cache
32 kB x 4
L2 Cache
1024 kB x 2
L3 Cache
not Present
64-bit
Supported
Limit CPUID Maximum
[Disabled]
Execute Disable Bit
[Enabled]
Hardware Prefetcher
[Enabled]
Adjacent Cache Line Prefetch
[Enabled]
Intel Virtualization Technology
[Enabled]
EIST
[Enabled]
Limit CPUID Maximum
The CPUID instruction of some newer CPUs will return a value greater
than 3. The default is Disabled because this problem does not exist in the
Windows series operating systems. If you are using an operating system
other than Windows, this problem may occur.
Execute Disable Bit
When this field is set to Disabled, it will force the XD feature flag to always
return to 0.
Hardware Prefetcher
Turns on or off the mid level cache (L2) streamer prefetcher.
Adjacent Cache Line Prefetch
Turns on or off prefetching of adjacent cache lines.
Intel
®
Virtualization Technology
When this field is set to Enabled, the VMM can utilize the additional
hardware capabilities provided by Vanderpool Technology.
EIST
Enables or disables Intel
®
SpeedStep.
