N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
39
Figure 3-32 PCM data output timing in auxiliary mode
AUX_PCM_CLK
AUX_PCM_SYNC
AUX_PCM_DOUT
(Companded)
MSB
MSB-1
LSB
AUX_PCM_DOUT
(Linear)
LSB+1
MSB
MSB-1
MSB-7
MSB-6
LSB
MSB-8 LSB+1
LSB
t(auxclk)
t(auxclkh)
t(hauxsync)
t(suauxsync)
t(pauxdout)
Table 3-8 Parameters of PCM timing in auxiliary mode
Timing Parameter
Minimum
Value
Typical
Value
Maximum
Value
Unit
t(auxsync)
PCM_SYNC cycle
/
125
/
ns
t(auxsynca)
PCM_SYNC valid time
62.4
62.5
/
ns
t(auxsyncd)
PCM_SYNC invalid time
62.4
62.5
/
ns
t(auxclk)
PCM_CLK cycle
/
7.8
/
us
t(auxclkh)
PCM_CLK high time
3.8
3.9
/
us
t(auxclkl)
PCM_CLK low time
3.8
3.9
/
us
t(suauxsync)
PCM_SYNC set-up time to PCM_CLK
rising
1.95
/
/
ns
t(hauxsync)
PCM_SYNC hold time after PCM_CLK
rising
1.95
/
/
ns
t(suauxdin)
PCM_DIN set-up time to PCM_CLK falling 70
/
/
ns
t(hauxdin)
Hold time from PCM_CLK low to
PCM_DIN high
20
/
/
ns
t(pauxdout)
Delay time from PCM_CLK PCM_DOUT
valid
/
/
50
ns
3.3.7 SPI
Signal
Pin I/O
Function
Remarks
SPI_CLK_BLSP2
84
DO Clock signal
Max. 50MHz
