N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
38
Table 3-7 Parameters of PCM timing in primary mode
Timing Parameter
Minimum
Value
Typical
Value
Maximum
Value
Unit
t(sync)
PCM_SYNC cycle
/
125
/
ns
t(synca)
PCM_SYNC valid time
/
488
/
ns
t(syncd)
PCM_SYNC invalid time
/
124.5
/
ns
t(clk)
PCM_CLK cycle
/
488
/
ns
t(clkh)
PCM_CLK high time
/
244
/
ns
t(clkl)
PCM_CLK low time
/
244
/
ns
t(susync)
Set-up time from PCM_SYNC high to
PCM_CLK low
/
122
/
ns
t(sudin)
Set-up time from PCM_DIN high to
PCM_CLK low
60
/
/
ns
t(hdin)
Hold time from PCM_CLK low to PCM_DIN
high
10
/
/
ns
t(pdout)
Delay time from PCM_CLK high to
PCM_DOUT low
/
/
60
ns
t(zdout)
Delay time from PCM_CLK low to
PCM_DOUT high impedance
/
160
/
ns
Figure 3-30 PCM sync signal timing in auxiliary mode
PCM_SYNC
t(auxsync)
t(auxsyncd)
t(auxsynca)
Figure 3-31 PCM data input timing in auxiliary mode
AUX_PCM_CLK
AUX_PCM_SYNC
AUX_PCM_DIN
(Companded)
MSB
MSB-1
LSB
MSB
MSB-1
MSB-2
LSB
MSB-8
LSB
AUX_PCM_DIN
(Linear)
t(auxclk)
t(auxclkh)
t(auxclkl)
t(suauxsync)
t(hauxsync)
t(suauxdin)
t(hauxdin)
