Neoway N720 Hardware User'S Manual Download

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N720 OpenLinux

Hardware User Guide

Figure 3-26 PCM connection ........................................................................................................... 37

Figure 3-27 PCM sync signal timing in primary mode ..................................................................... 37

Figure 3-28 PCM data input timing in primary mode ....................................................................... 37

Figure 3-29 PCM data output timing in primary mode ..................................................................... 37

Figure 3-30 PCM sync signal timing in auxiliary mode .................................................................... 38

Figure 3-31 PCM data input timing in auxiliary mode ...................................................................... 38

Figure 3-32 PCM data output timing in auxiliary mode .................................................................... 39

Figure 3-33 SPI connection .............................................................................................................. 40

Figure 3-34 SPI timing ..................................................................................................................... 41

Figure 3-35 I2Cconnection ............................................................................................................... 42

Figure 3-36 I2C data transmission ................................................................................................... 42

Figure 3-37 I2C timing ...................................................................................................................... 43

Figure 3-38 SGMII connection ......................................................................................................... 45

Figure 3-39 Connection between MDIO and PHY ........................................................................... 47

Figure 3-40 MDIO input timing ......................................................................................................... 47

Figure 3-41 MDIO output timing ....................................................................................................... 47

Figure 3-42 WLAN connection ......................................................................................................... 49

Figure 3-43 SDIO SDR timing .......................................................................................................... 50

Figure 3-44 SDIO DDR timing .......................................................................................................... 50

Figure 3-45 Bluetooth connection .................................................................................................... 52

Figure 3-46 L network ...................................................................................................................... 53

Figure 3-47 Split capacitor network.................................................................................................. 53

Figure 3-48 Pi network ..................................................................................................................... 54

Figure 3-49 Recommended RF PCB design 1 ................................................................................ 55

Figure 3-50 Recommended RF PCB design 2 ................................................................................ 55

Figure 3-51 GNSS RF structure ....................................................................................................... 55

Figure 3-52 Reference Design of Passive GNSS Antenna .............................................................. 56

Figure 3-53 Reference design of active GNSS antenna .................................................................. 57

Figure 3-54 Reference layout of GNSS antenna traces .................................................................. 58

Figure 3-55 Specifications of MM9329-2700RA1 ............................................................................ 59

Figure 3-56 RF connections ............................................................................................................. 59

Summary of Contents for N720

Page 1: ...N720 OpenLinux Hardware User Guide Issue 1 4 Date 2019 03 25 Neoway Product Document...

Page 2: ...PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT O...

Page 3: ...Peripheral Interfaces 24 3 3 2 USB 24 3 3 3 USIM 26 3 3 4 UART 27 3 3 5 SDC 31 3 3 6 I2S PCM 35 3 3 7 SPI 39 3 3 8 I2C 41 3 4 Network and Connection 45 3 4 1 Ethernet 45 3 4 2 WLAN 48 3 4 3 Bluetooth...

Page 4: ...4 6 2 Label 75 6 3 Pack 75 6 3 1 Tray 76 6 3 2 Moisture 77 7 Mounting N720 onto the Application Board 78 7 1 Bottom Dimensions 78 7 2 Application Foot Print 79 7 3 Stencil 79 7 4 Solder Paste 79 7 5 S...

Page 5: ...re 3 9 N720 on off timing 22 Figure 3 10 Reset controlled by button 23 Figure 3 11 Reset circuit with triode separating 23 Figure 3 12 Reset timing of N720 OpenLinux 23 Figure 3 13 USB connection 25 F...

Page 6: ...igure 3 37 I2C timing 43 Figure 3 38 SGMII connection 45 Figure 3 39 Connection between MDIO and PHY 47 Figure 3 40 MDIO input timing 47 Figure 3 41 MDIO output timing 47 Figure 3 42 WLAN connection 4...

Page 7: ...process 65 Figure 3 61 Outgoing call service process 65 Figure 3 62 Process of exiting from sleep mode 65 Figure 3 63 Reference design of USB_BOOT 66 Figure 6 1 N720 dimensions 74 Figure 6 2 N720 Ope...

Page 8: ...es 36 Table 3 7 Parameters of PCM timing in primary mode 38 Table 3 8 Parameters of PCM timing in auxiliary mode 39 Table 3 9 Timing parameters of SPI interface 41 Table 3 10 I2C feature parameters 41...

Page 9: ...u have any question or doubt Audience This document is intended for system engineers SEs development engineers and test engineers Change History Issue Date Change Changed By 1 0 2017 02 Initial draft...

Page 10: ...Symbol Indication This warning symbol means danger You are in a situation that could cause fatal device damage or even bodily damage Means reader be careful In this situation you might perform an act...

Page 11: ...inux series include multiple variants Table 1 1 lists the variants and frequency bands supported Table 1 1 Variant and frequency bands Version Region Category Band GNSS1 CA China Cat4 FDD LTE B1 B3 B5...

Page 12: ...7 UMTS B2 B4 B5 GSM GPRS EDGE 850 900 1800 1900 MHz support TWN Taiwan Cat4 FDD LTE B1 B3 B7 B8 B28 UMTS B1 B8 GSM GPRS EDGE 900 1800 MHz support 1 2 Block Diagram N720 OpenLinux consists of the follo...

Page 13: ...ORY SUPPORT RFFE I F S CONNECTIVITY SPMI VDDs TRX TRX MIPI Input PM Output PM Interfaces ADC PM_GPIOs VBAT UART SPI I2C ADC USB SGMII SDIO UIM GPIO I2S PCM Power Manager VDDs for MCP VDDs for PA ASW 1...

Page 14: ...ass 4 EGSM900 33dBm Power Class 4 DCS1800 30dBm Power Class 1 PCS1900 30dBm Power Class 1 EDGE 850MHz 27dBm Power Class E2 EDGE 900MHz 27dBm Power Class E2 EDGE1800MHz 26dBm Power Class E2 EDGE1900MHz...

Page 15: ...x 50 Mbps One USIM interface 1 8V 2 85V One USB2 0 interface OTG function requires external 5V DC DC Two 15 bit ADC interfaces detectable voltage ranging from 0 1 to 1 7V One I2S PCM interface used to...

Page 16: ...ght Neoway Technology Co Ltd 6 2 Module Pins There are 100 pins on N720 OpenLinux and their pads are introduced in LGA package 2 1 Pad Layout Figure 2 1 shows the pad layout of N720 OpenLinux Figure 2...

Page 17: ...Pin type Voltage Feature Current Feature P1 USIM1 interface voltage compatible with 1 8V 2 85V 1 8V Voltage Feature VIH 1 26V 2 1V VIL 0 3V 0 36V VOH 1 44V 1 8V VOL 0V 0 4V 2 85V Voltage Feature VIH 2...

Page 18: ...45V VIO is GPIO voltage 1 2V 1 8V VBAT When VIO is 1 8V High 0 9mA Medium 0 6mA Low 0 15 mA P8 Level of GPIO for power management chipset fixed to 1 8V VIH 1 26V 2 1V VIL 0 3V 0 63V VOH 1 35V 1 8V VOL...

Page 19: ...WRKEY_P 34 DI Module ON OFF control P3 Triggered by high level Embedded a 200 k pull down resistor Connect it to the ground plane if it is not used UART Interface UART5_TXD 46 DO UART5 data transmitti...

Page 20: ...tectable voltage ranging from 0 1V to 1 7V Leave this pin floating if it is not used ADC1 89 AI Analog to digital signal conversion Vmax 1 7V Vmin 0 1V 15 bit detectable voltage ranging from 0 1V to 1...

Page 21: ...Leave this pin floating if it is not used I2S_1_DOUT 10 DO I2S data transmit P3 I2S_1_DIN 11 DI I2S data receive P3 I2S_1_WS 12 B I2S word select P3 I2S_MCLK 64 DO I2S main clock P3 12 288 MHz by defa...

Page 22: ...nload mode control P3 Do not pull this pin high during the startup of the module Otherwise the module enters USB_BOOT mode WCI_LTE_TXD 50 DO LTE WLAN co exist UART data transmit P3 Leave this pin floa...

Page 23: ...SDC data1 IO P4 SDC_DET 96 DI SD card detect P3 Leave this pin floating if it is not used SPI interface SPI_CLK_BLSP2 84 DO Clock signal P3 Used only in host mode Leave these pins floating if they are...

Page 24: ...faces RING 13 DO Incoming call SMS indicator P3 Leave this pin floating if it is not used DTR 79 DI Sleep mode control P3 Leave this pin floating if it is not used OTG_5V_EN 80 DO External 5V power en...

Page 25: ...V TYP 3 8V VDDIO_1P8 45 PO 1 8V power output Output 50 mA at most used only for level shifting Add ESD protector when using this pin VDDXO_1P8 53 PO 1 8V power output Used only to connect WLAN oscilla...

Page 26: ...ematic Design Design the circuit of the power supply for N720 OpenLinux based on the input voltage you choose Generally there are three types of input voltages 3 3V 4 3V 3 8V typically output by batte...

Page 27: ...ter out high frequency noise from the power supply A controllable power supply is preferable if the module is used in harsh conditions Figure 3 3 shows the recommended schematic design Figure 3 3 Reco...

Page 28: ...ommended for 5 5V 24V input Figure 3 5 Recommended design 4 VIN EN RT CLK P PAD GND BOOST SW FB COMP R1 47 5k 12k 100pF 0 01uF L1 3 3uH 0 1uF 470uF 1k 47 5k 12k SS36 VIN 5 5V 42V C1 100uF C2 22uF C3 0...

Page 29: ...er foil under all VBAT pins and connect the pins to the power supply through via holes Place TVS diodes as close to the power input interface as possible to ensure that the surge voltage can be clampe...

Page 30: ...ESET_N 32 DI Module reset input Reset at low level PWRKEY_N 33 DI ON OFF button Triggered by low level recommended PWRKEY_P 34 DI ON OFF button Triggered by high level N720 OpenLinux provides two PWRK...

Page 31: ...SD N720 module PWRKEY_N S1 R1 1k Figure 3 7 Reference design of startup controlled by MCU R1 N720 module PWRKEY_N R2 USER_ON Q1 Figure 3 8 Reference design of automatic start once powered up 1 5 k N72...

Page 32: ...l it is initialized completely If the module is powered up but the startup process has not been completed the states of each pin are uncertain Shutdown Process The module can be powered off in two way...

Page 33: ...pin floating if not used If you use a 2 8V 3 0V 3 3V IO system it is recommended to add a triode to separate it Refer to the following designs To reset the module through high level refer to Figure 3...

Page 34: ...ober 2012 SGMII MDIO ENG 46158 Rev 1 8 IEEE 802 3 2002 Part 3 IEEE 1588 2008 In all reference designs of this section the signals of pins on the module is named in perspective of module while peripher...

Page 35: ...ID USB Device USB_ID USB_DP USB_DM USB_VBUS N720 module ESD4 C4 C5 5V DC DC VCC IN EN OTG_5V_EN OUT Schematic Design Recommendations Connect a 1 F and a 22pF filter capacitors in parallel to the USB_V...

Page 36: ...gnal Pin I O Function Remarks USIM1_VCC 35 PO USIM1 power output Compatible with 1 8V 3V UIM card USIM1_DATA 36 B USIM data IO A 10 k resistor is required between USIM1_VCC and USIM1_DATA USIM1_CLK 37...

Page 37: ...e USIM_DET pin before and after a UIM card is inserted In the reference circuit USIM DET is floating before a USIM card is inserted and is grounded after a USIM card is inserted Low level means USIM c...

Page 38: ...design of UART connection without flow control UART5_RXD UART5_TXD MCU_TXD MCU_RXD GND GND N720 module Client Schematic Design Recommendations Note the match of signals If the UART does not match the...

Page 39: ...ing circuit 1 MCU_RXD MCU_TXD UART_TXD VDD_1P8 VCC_IO 4 7k 10k Q1 R2 R1 VDD_1P8 VCC_IO 4 7k 10k Q2 R3 R4 MCU_RXD If the low level at MCU_UART VIL is lower than 200mV adopt recommended level shifting c...

Page 40: ...R12 R7 R8 R11 R10 C1 C2 220pF UART_TXD 10k R2 4 7k VDD_1P8 2 2 k 220pF 47k 4 7k Q1 Q2 MCU_RXD VCC_IO R5 R6 R3 R1 R4 47k MCU_TXD and MCU_RXD are respectively the TX and RX of the MCU while UART_TXD an...

Page 41: ...to 5 5V EN is the enable pin which works at a voltage of greater than VL 0 2V In the above circuit the EN pin is connected to VDD_1P8 and the level shifter is always working PCB Design Guidelines Do...

Page 42: ...21 SD connection SDC_CLK SDC_CMD SDC_DATA0 SDC_DATA1 N720 module SD connector SDC_DATA2 SDC_DATA3 SDC_DET SDC_PWR_EN VCC CLK CMD DATA0 DATA1 DATA2 DATA3 DET VDD_SDC_IO VDD_1P8 10k 47k SDC Power 10k 1...

Page 43: ...s an option In Figure 3 21 ESD1 and ESD2 consist of four same ESD protectors PCB Design Guidelines Place ESD protectors close to SD connector The pin numbers of ESD arrays can be adjusted in actual ap...

Page 44: ...l Value Maximum Value Unit SDR mode max 200MHz t cvdrd Command valid time 2 4 ns t dvdrd Data valid time 2 4 ns t pddwr Delay time from data write to transmit 1 36 0 76 ns t pdcwr Delay time from comm...

Page 45: ...connection Figure 3 24 I2S connection I2S_TX I2S_RX I2S_WS I2S_SCLK N720 module Codec I2S_MCLK I2S_MCLK I2S_DIN I2S_DOUT I2S_LRCLK I2S_BCLK Schematic Design Recommendations If the levels of N720 OpenL...

Page 46: ...time 0 45 T 0 55 T ns t LC Clock low time 0 45 T 0 55 T ns t sr Set up time from data receive to WS input 16 276 ns t hr Hold time from data receive to WS input 0 ns t dtr Delay time from data send t...

Page 47: ...are the same as those of I2S The PCM interface supports only standard modes Figure 3 27 PCM sync signal timing in primary mode PCM_SYNC t sync t syncd t synca Figure 3 28 PCM data input timing in prim...

Page 48: ...CM_SYNC high to PCM_CLK low 122 ns t sudin Set up time from PCM_DIN high to PCM_CLK low 60 ns t hdin Hold time from PCM_CLK low to PCM_DIN high 10 ns t pdout Delay time from PCM_CLK high to PCM_DOUT l...

Page 49: ...Value Unit t auxsync PCM_SYNC cycle 125 ns t auxsynca PCM_SYNC valid time 62 4 62 5 ns t auxsyncd PCM_SYNC invalid time 62 4 62 5 ns t auxclk PCM_CLK cycle 7 8 us t auxclkh PCM_CLK high time 3 8 3 9...

Page 50: ...SPI_CS_N SPI_CLK N720 module host SPI_MISO MOSI MISO CLK CS SPI device device Schematic Design Recommendations Note the SPI signal direction If the levels of slave SPI device and N720 OpenLinux do no...

Page 51: ...ernally I2C_4_SCL 82 DO I2C clock Embed a 2 2 k pulled up resistor internally I2C operates at 1 8V and complies with I2C Specification version5 0 October 2012 Theoretical rate is up to 1 Mbps The I2C...

Page 52: ...can be multiplexed for I2C function Connect external pull up resistors to these pins when they are used for I2C function For details see section 3 7 MUX Interfaces PCB Design Guidelines Do not cross o...

Page 53: ...ondition 4 0 us tLOW LOW period of the SCL pin 4 7 us tHIGH HIGH period of the SCL pin 4 0 5 0 us tSU STA Set up time for a repeated START condition 4 7 us tHD DAT Data hold time 0 us tSU DAT Data set...

Page 54: ...time for SCL and SDA 6 55 300 ns tSU STO Set up time for STOP condition 0 6 us tBUF Bus free time between STOP and START condition 1 3 us tVD DAT Data invalid time 0 9 us tVD ACK Data invalid acknowle...

Page 55: ...if it is not used SGMII_TX_P 16 AO SGMII transmit plus Leave this pin floating if it is not used SGMII_RX_N 18 AI SGMII receive minus Leave this pin floating if it is not used SGMII_RX_P 19 AI SGMII...

Page 56: ...impedance of the TX and RX traces separately and the differential impedance ranges from 80 to 120 Trace spacing between TX and RX should be larger than 3x trace widths Trace spacing between SGMII and...

Page 57: ...IM2_VCC 1 5k 10k VDD_1P8 R1 R2 U1 MDIO can control one MAC or up to 32 PHY devices It supports a maximum frequency of 2 5 MHz and 1 8V 2 85V auto adaption Figure 3 40 and Figure 3 41 show MDIO input o...

Page 58: ...AN_SDIO_CLK 55 DO Clock signal output of SDIO interface WLAN_SDIO_DATA0 56 B SDIO data bit 0 WLAN_SDIO_DATA1 57 B SDIO data bit 1 WLAN_SDIO_DATA2 58 B SDIO data bit 2 WLAN_SDIO_DATA3 59 B SDIO data bi...

Page 59: ...e VDD_1P8 of OpenLinux module and the pull up resistor uses the recommended values WLAN LTE co exist interface is used for 2 4 GHz WLAN frequency band and LTE high frequency which overlap so they migh...

Page 60: ...AN interface Timing Parameter Minimum Value Typical Value Maximum Value Unit SDR mode max 200MHz t cvdrd Command valid time 2 4 ns t dvdrd Data valid time 2 4 ns t pddwr Delay time from data write to...

Page 61: ...T_UART_TXD 69 DO Data TX of Bluetooth UART Used for Bluetooth data transmission Leave them floating if they are not used BT_UART_RXD 70 DI Data RX of Bluetooth UART BT_UART_CTS 71 DI Clear to send BT_...

Page 62: ...able pin The Bluetooth is controlled by UART Ensure the match of UART signals and logic levels BT_WAKEUP_SLAVE is the control signal for the module to wake up the Bluetooth chipset Add a pull up resis...

Page 63: ...require a characteristic impedance of 50 Developers should control the impedance of the traces between the pins and antenna to ensure the RF performance An impedance matching circuit such as L network...

Page 64: ...recommended PCB Design Guidelines Lay copper foil around RF connector Dig as many ground holes as possible on the copper to ensure lowest grounding impedance The trace between N720 OpenLinux and the...

Page 65: ...ure 3 50 Recommended RF PCB design 2 3 5 2 ANT_GNSS Interface GPS Impedance Control ANT_GNSS 92 is the GNSS RF interface of N720 OpenLinux which requires a characteristic impedance of 50 Figure 3 51 s...

Page 66: ...e module does not embed one internally GNSS_LNA_EN is used to enable the external LNA To get a better performance use a multi stage LNA Add a SAW filter between matching network and LNA PCB Design Gui...

Page 67: ...requency jamming signal An inductor of 47 nH to 100 nH is recommended at L1 C1 is a DC blocking capacitor and its capacitance is 33 pF or 100 pF Z1 Z2 and Z3 form a matching network see section 3 5 1...

Page 68: ...anges from 1 1 to 1 5 and the input input impedance is 50 Antenna should be well matched to achieve best performance in different application scenarios Antenna interfaces can be connected to rubber du...

Page 69: ...Remarks GPIO_76 68 B GPIO with interrupt GPIO_77 67 B GPIO without interrupt GPIO_78 66 B GPIO without interrupt Do not pull this pin high before the module is started GPIO_79 65 B GPIO with interrup...

Page 70: ...1_DIN GPIO_21 UART6_RXD SPI_MISO_BLSP6 PCM1_DIN Y 12 I2S_1_WS GPIO_20 UART6_TXD SPI_MOSI_BLSP6 PCM1_SYNC Y 22 SGMII_MDIO_CLK GPIO_27 USIM2_DATA GP_CLK_1A8 N 23 SGMII_MDIO_DATA GPIO_28 USIM2_CLK GP_CLK...

Page 71: ...WLAN_SDIO_CLK GPIO_16 UART4_TXD SPI_MOSI_BLSP4 Y 56 WLAN_SDIO_DATA0 GPIO_15 UART1_RTS I2C_SCL_BLSP1 SPI_CLK_BLSP1 57 WLAN_SDIO_DATA1 GPIO_14 UART1_CTS I2C_SDA_BLSP1 SPI_CS_N_BLSP1 GP_CLK_1B 58 WLAN_S...

Page 72: ...IO_75 Y 80 OTG_5V_EN GPIO_247 81 I2C_4_SDA GPIO_18 UART4_CTS SPI_CS_N_BLSP4 82 I2C_4_SCL GPIO_19 UART4_RTS SPI_CLK_BLSP4 83 NET_LIGHT GPIO_74 Y 84 SPI_CLK_BLSP2 GPIO_7 UART2_RTS I2C_SCL_BLSP2 85 SPI_M...

Page 73: ...tal signal conversion The module provides two ADC channels and the input voltage ranges from 0 1V to 1 7V The ADC pins support a highest precision of 15 bit and it can be used for temperature detectio...

Page 74: ...n respond to the incoming calls SMS and GPRS data The following figures show processes of entering sleep mode service processes in sleep mode and process of exiting from sleep mode when an external MC...

Page 75: ...ed Forbid sleep mode Exits from sleep mode Sleep mode MCU detects information from UART MCU pulls SLEEP pin to high End Enable UART and process services MCU pulls SLEEP pin to low Wait till services a...

Page 76: ...unning failures Connect USB_BOOT to VDDIO_1P8 through a pull up resistor transiently after the module is started and the module will enter forcible download mode Reserve this pin to facilitate softwar...

Page 77: ...ge burst during the startup the module might be damaged permanently If you use LDO or DC DC to supply power for the module ensure that it outputs at least 2 A current When the module works at maximum...

Page 78: ...ESD capability of key pins of this module It is recommended to add ESD protection based on the application scenarios to ensure product quality when designing a product Humidity 45 Temperature 25 Tabl...

Page 79: ...1710 1785MHz 1805 1880MHz PCS1900 1850 1910MHz 1930 1990MHz CDMA BC0 824 849MHz 869 894MHz UMTS B1 1920 1980MHz 2110 2170MHz UMTS B2 1850 1910MHz 1930 1990MHz UMTS B4 1710 1755MHz 2110 2155MHz UMTS B5...

Page 80: ...X Power and RX Sensitivity Table 5 2 RF TX power Band Max Power Min Power GSM850 33 dBm 2 2dB 5 dBm 2 2 dBm EGSM900 33 dBm 2 2dB 5 dBm 2 2 dBm DCS1800 30 dBm 2 2dB 0 dBm 2 2 dBm PCS1900 30 dBm 2 2 dB...

Page 81: ...40 dBm FDD LTE B28A 23 dBm 2 2 dBm 40 dBm FDD LTE B28B 23 dBm 2 2 dBm 40 dBm TDD LTE B38 23 dBm 2 2 dBm 40 dBm TDD LTE B39 23 dBm 2 2 dBm 40 dBm TDD LTE B40 23 dBm 2 2 dBm 40 dBm TDD LTE B41 23 dBm 2...

Page 82: ...95 dBm All values above were obtained in the lab In actual applications there might be a difference because of network environments 5 3 GNSS Feature Changes Parameter GPS L1 operating frequency 1575...

Page 83: ...515 m s Max positioning acceleration 4g GNSS data type NMEA 0183 GNSS antenna type Passive active antenna Tracking sensitivity acquisition sensitivity and re acquisition sensitivity were obtained in s...

Page 84: ...nLinux Hardware User Guide Copyright Neoway Technology Co Ltd 74 6 Mechanical Features This chapter describes the mechanical features of N720 OpenLinux 6 1 Dimensions Figure 6 1 N720 dimensions The un...

Page 85: ...up to 260 C Figure 6 2 N720 Openlinux label The picture above is only for reference The silk screen printing must be clear No blur is allowed The material and surface finishing must comply with RoHS...

Page 86: ...N720 OpenLinux Hardware User Guide Copyright Neoway Technology Co Ltd 76 6 3 1 Tray Figure 6 3 N720 OpenLinux packing with vacuum bag and tray Figure 6 4 Packaging process...

Page 87: ...liance with IPC JEDEC J STD 020 standard If the module is exposed to air for more than 48 hours at conditions not worse than 30 C 60 RH bake it at a temperature higher than 90 degree for more than 12...

Page 88: ...LGA package This chapter describes N720V5 foot print recommended PCB design and SMT information to guide users how to mount the module onto application PCB board 7 1 Bottom Dimensions Figure 7 1 Botto...

Page 89: ...pends on the solder paste volume and the PCB flatness Do not use the kind of solder paste different from our module technique The melting temperature of solder paste with lead is 35 C lower than that...

Page 90: ...90 s Peak temperature 235 250 C Neoway will not provide warranty for heat responsive element abnormalities caused by improper temperature control For information about cautions in N720 OpenLinux stora...

Page 91: ...as hospital or airplane where it might interfere with other electronic equipment Please follow the requirements below in application design Do not disassemble the module without permission from Neowa...

Page 92: ...nd to comply with the limits for class A digital devices These limits are designed to provide reasonable protection against harmful interference in a residential installation A 2 2 Environmental Prote...

Page 93: ...gation Satellite System GPIO General Purpose Input Output GPRS General Packet Radio Service HSPA High Speed Packet Access I2C Interintegrated Circuit I2S Inter IC Sound LGA Land Grid Array LTE Long Te...

Page 94: ...onous receiver transmitter USIM Universal Subscriber Identity Module UMTS Universal Mobile Telecommunications System USB Universal Serial Bus USB OTG Universal serial bus on the go WCDMA Wide band Cod...

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