44
NED
RMSL4K100CP
UME-0114-01
4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Video Data
From Sensor
-
x
Bright image reference
multiplication
Dark image reference
subtract
x
Digital Gain
Value Set
+/-
Digital Offset
Value Set
Scan Direction select
8 or 10bit select &
Test Patter select
Flat Field Correction
Digital Gain & Offset
Output Format
Video(8 or 10bit)
To Channel Link Driver
Figure 4-3-1 FPGA Processing Block Diagram
4.4 Startup
After turning on, the camera run a startup procedure before it starts getting images
and outputting data.
It takes about 3 seconds.
The startup procedure is as follows.
(1) The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory.
(User settings if any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After those sequences, the camera is ready to get images and output data.
In order to output camera control and images, it is necessary to perform device
discovery from the grabber board.
