NEC V850E/PH2, User Manual

Page: 89 / 1053

89
Chapter 3 CPU Functions
User’s Manual U16580EE3V1UD00
(1) Interrupt status saving registers (EIPC, EIPSW)
There are two context saving registers, EIPC and EIPSW.
Upon occurrence of a software exception or a maskable interrupt, the content of the program
counter (PC) is saved to EIPC and the content of the program status word (PSW) is saved to
EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI
status saving registers (FEPC, FEPSW)).
The address of the next instruction following the instruction executed when a software exception or
maskable interrupt occurs is saved to EIPC, except for the DIVH instruction (see Chapter
7
”Interrupt/Exception Processing Function” on page 219).
Since there is only one set of interrupt status saving registers, the contents of these registers must
be saved by the program when multiple interrupt servicing is enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function
expansion.
Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW)
The values of EIPC and EIPSW are restored to PC and PSW during execution of a RETI
instruction.
31 26 25 0
After reset
0xxxxxxxH
(x: Undefined)
EIPC 0 0 0 0 0 0 (PC contents)
31 8 7 0
After reset
000000xxH
(x: Undefined)
EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents)