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Chapter 8
Clock Generator
Preliminary User’s Manual U14913EE1V0UM00
8.7 Securing Oscillation Stabilization Time
8.7.1 Oscillation stabilization time security specification
Two methods can be used to secure the required stabilization times from when watch mode or software
STOP mode is released.
(1)
Securing the time using an on-chip time base counter
Watch mode and software STOP mode are released when a valid edge is input to the NMI pin or a
maskable interrupt request is input (INTPn). Valid edge input to the pin causes the time base coun-
ter (TBC) to start counting, and the time until the clock output from the oscillator stabilizes is
secured during that counting time.
Oscillation stabilization time = TBC counting time
After a fixed time, internal system clock output begins, and processing branches to the NMI inter-
rupt or maskable interrupt (INTPn) handler address.
Figure 8-4: WATCH mode release by NMI or INT
Watch mode setting
Oscillation circuit
System clock
Watch state
NMI or INT input
Watch clock working
Time base counter's
counting time
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