CHAPTER 7 NOTES ON TARGET SYSTEMS
User’s Manual U17454EJ1V0UM
68
CPU Pin
Design Proposal
RESET
•
Connection to a point where the target CPU RESET pin cannot be driven to low level by the FPL3 RESET
signal.
Incorrect connection:
A
CPU
FPL3 RESET
RESET
When the FPL3 RESET is driven low, the level of the voltage at point A does not fall.
Serial
interface pin
When the CPU port used by the FPL3 is also connected to the input of an external device, and if that device
malfunctions, disconnect the external device or make it output high impedance.
Example:
Adverse effect
FP4
connector
Input
External device
CPU
S0/TxD
While the CPU port used by the FPL3 is also connected to the output of an external device, and if a signal
collision occurs, disconnect the external device.
Example:
FP4
connector
Collision
Output
External device
CPU
S1/RxD
Other
For the unused pins, refer to the user’s manual of the device.
