NEC MuPD70F3187, User Manual

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Chapter 17 Clocked Serial Interface 3 (CSI3)
User’s Manual U16580EE3V1UD00
17.5.14 Delay control of transmission/reception completion interrupt (INTC3n)
In the master mode (CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B), occurrence of
the transmission/reception completion interrupt (INTC3n) can be delayed by half a clock (1/2 serial
clock), depending on the setting of the CSITn bit of the CSIM3n register (CSITn bit = 1). The CSITn bit
is valid only in the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111B), setting the CSITn
bit to 1 is prohibited (even if set, the INTC3n interrupt is not affected).
Caution: If the CSITn bit of the CSIM3n register is set to 1 in the consecutive mode (TRMDn bit
of the CSIM3n register = 1), the INTC3n interrupt is not output at the end of data other
than the last data set by the SFNn3 to SFNn0 bits of the SFN3n register, but a delay of
half a clock can be inserted between each data transfer.
Figure 17-20: Delay Control of Transmission/Reception Completion Interrupt (INTC3n):
CSITn Bit of the CSIM3n Register = 1,
CSWEn Bit of the CSIM3n Register = 0,
CKPn and DAPn Bits of the CSIC3n Register = 00B,
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits of the CSIL3n Register = 1000B)
Remark:
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
DI7 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Delay
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO7
SCK3n (output)
SI3n (input)
SO3n (output)
INTC3n interrupt
Delay