NEC MuPD70F3187, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
11.6 Operation in Each Mode
11.6.1 Interval timer mode
In the interval timer mode, a compare match interrupt (INTTTnCC0) occurs and the counter is cleared
upon a match between the setting value of the TTnCCR0 register and the counter value. The
occurrence interval for this counter and TTnCCR0 register match interrupt becomes the interval time.
In the interval timer mode, the counter is cleared only upon a match between the counter and the value
of the TTnCCR0 register. Counter clearing using the TTnCCR1 register is not performed.
However, the setting value of the TTnCCR1 is compared to the counter value transferred to the
TTnCCR1 buffer register and a compare match interrupt (INTTTnCC1) is output.
The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method, regardless of
the value of bit TTnCE.
Pins TOTn0 and TOTn1 are toggle output controlled when bits TTnOE0 and TTnOE1 are set to 1.
Figure 11-20: Basic Operation Flow in Interval Timer Mode
Note: In the case of a match between the counter and TTnCCR1 register, the counter is not cleared.
START
Initial settings
•
Clock selection
(TTnCTL0: TTnCKS2 to TTnCKS0)
•
Interval mode setting
(TTnCTL1: TTnMD3 to TTnMD0 = 0000)
•
Compare register setting
(TTnCCR0, TTnCCR1)
Timer operation enable (TTnCE = 1)
Transfer of TTnCCR0 and TTnCCR1
values to TTnCCR0 and TTnCCR1 buffers
Match between counter and TTnCCR1
buffer value
Note
Match between counter and
TTnCCR0 buffer value, counter
clear & start
INTTTnCC1
occurrence
INTTTnCC0
occurrence
→