NEC MuPD70F3187, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
10.10 Operation in Each Mode
10.10.1 Interval timer mode
(1) Outline of interval timer mode
In the interval timer mode, a compare match interrupt (INTTRnCC0) occurs and the counter is
cleared upon a match between the setting value of the TRnCCR0 register and the counter value.
The occurrence interval for this counter and TRnCCR0 register match interrupt becomes the
interval time.
In the interval timer mode, the counter is cleared only upon a match between the counter and the
value of the TRnCCR0 register. Counter clearing using the TRnCCR1 to TRnCCR5 registers is
not performed.
However, the setting values of the TRnCCR1 to TRnCCR5 registers are compared to the counter
values transferred to the TRnCCR1 to TRnCCR5 buffer registers and compare match interrupts
(INTTRnCC1 to INTTRnCCR5) are output.
The TRnCCR0 to TRnCCR5 registers can be rewritten using the anytime write method, regardless
of the value of bit TRnCE.
Pins TORn0 to TORn7 are toggle output controlled when bits TRnOE0 to TRnOE7 are set to 1.
Figure 10-41: Basic Operation Flow in Interval Timer Mode
Note: In the case of a match between the counter and TRnCCR1 to TRnCCR5 registers, the counter
is not cleared.
START
Initial settings
•
Clock selection
(TRnCTL0: TRnCKS2 to TRnCKS0)
•
Interval mode setting
(TRnCTL1: TRnMD3 to TRnMD0 = 0000)
•
Compare register setting
(TRnCCR0 to TRnCCR5)
Timer operation enable (TRnCE = 1)
→
Transfer of TRnCCR0 to TRnCCR5
values to TRnCCR0 to TRnCCR5 buffers
Match between counter and TRnCCR1 to
TRnCCR5 buffer values
Note
Match between counter and
TRnCCR0 buffer value, counter
clear & start
INTTRnCC1 to
INTTRnCC5
occurrence
INTTRnCC0
occurrence