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Chapter 3
CPU Functions
User’s Manual U16580EE3V1UD00
3.4.8 Specific
registers
Specific registers are registers that prevent invalid data from being written if an inadvertent program
behaviour occurs.
The V850E/PH2 has the following specific registers:
•
Port registers 5 and 6 (P5, P6)
•
Port mode registers 5 and 6 (PM5, PM6)
•
Port mode control registers 5 and 6 (PMC5, PMC6)
•
Port emergency shut off control registers 5 and 6 (PESC5, PESC6)
•
Port emergency shut off status registers 5 and 6 (ESOST5, ESOST6)
Moreover, there is also a command register (PRCMD), which is a protection register against write
operations to the specific registers. Write access to the specific registers is performed with a special
sequence and illegal store operations are notified to the system status register (PHS).
This section of the manual describes the access method to these specific registers, rather than the
values that can be written to these registers. For details on these register values, please refer to
sections
(1)
Setting data to specific registers
Setting data to a specific registers is done in the following sequence.
<1>
Prepare the data to be set to the special register in a general-purpose register.
<2>
Write the data prepared in <1> to the command register (PRCMD).
<3>
Write the data to the specific register (using the following instructions).
•
Store instruction (ST/SST instruction)
•
Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
Example
<1> MOV 0x02, r10
; Prepare data in r10
<2> ST.B r10, PRCMD[r0]
; Write PRCMD register
<3> ST.B r10, P5
; Set P5 register
(next instruction)
Cautions: 1. Interrupts are not acknowledged when executing the store instruction to the
PRCMD register.
If another instruction is placed between steps <2> and <3>, the correct sequence
may not be realized if an interrupt is acknowledged for that instruction, resulting
in the writing to the protected register to be not done, and an error to be stored in
the PRERR bit of the PHS register.
2. If there is a possibility of an active DMA register before <2> and <3>, the specific
register may not be written. In this case, ensure that no DMA register is active
during the sequence <2> to <3>, or repeat the sequencer <2> to <3> as long as
the PRERR bit of the PHS register is set to <1>.
Summary of Contents for MuPD70F3187
Page 6: ...6 Preface User s Manual U16580EE3V1UD00 ...
Page 16: ...16 User s Manual U16580EE3V1UD00 ...
Page 28: ...28 User s Manual U16580EE3V1UD00 ...
Page 32: ...32 User s Manual U16580EE3V1UD00 ...
Page 84: ...84 Chapter 2 Pin Functions User s Manual U16580EE3V1UD00 MEMO ...
Page 144: ...144 Chapter 3 CPU Functions User s Manual U16580EE3V1UD00 MEMO ...
Page 312: ...312 Chapter 9 16 Bit Timer Event Counter P User s Manual U16580EE3V1UD00 MEMO ...
Page 534: ...534 Chapter 11 16 bit Timer Event Counter T User s Manual U16580EE3V1UD00 ...
Page 969: ...969 Chapter 20 Port Functions User s Manual U16580EE3V1UD00 MEMO ...
Page 970: ...970 Chapter 20 Port Functions User s Manual U16580EE3V1UD00 ...
Page 976: ...976 Chapter 22 Internal RAM Parity Check Function User s Manual U16580EE3V1UD00 MEMO ...
Page 984: ...984 Chapter 23 On Chip Debug Function OCD User s Manual U16580EE3V1UD00 MEMO ...
Page 1006: ...1006 Chapter 24 Flash Memory User s Manual U16580EE3V1UD00 MEMO ...
Page 1036: ...1036 Chapter 27 Recommended Soldering Conditions User s Manual U16580EE3V1UD00 MEMO ...
Page 1046: ...1046 Appendix A Index User s Manual U16580EE3V1UD00 MEMO ...
Page 1052: ...1052 User s Manual U16580EE3V1UD00 ...
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