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NEC Advanced Personal Computer, System Reference Manual

Introducing the NEC Advanced Personal Computer, a versatile and powerful computing device. Unlock its full potential by downloading the comprehensive System Reference Manual – a must-have guide for every user. Explore detailed instructions, troubleshooting tips, and much more, all available for free download at manualshive.com. Empower yourself with this essential manual today!

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Summary of Contents for Advanced Personal Computer

Page 1: ...NEe ...

Page 2: ... Advanced A Personal Computer TM APe System Reference Guide NEe NEe Information Systems Inc 819 000100 1003 4 83 ...

Page 3: ...e determined by the customer and is not warranted by NEC Information Systems Inc This manual is as complete and factual as possible at the time ofprinting however the information in this manual may have been updated since that time NEC Information Systems Inc reserves the right to change the functions features or specifications of its products at any time without notice NEC Information Systems Inc...

Page 4: ...installing and operating this device 1 Operate the equipment in strict accordance with the manufacturer s instructions for the model 2 Ensure that the unit is plugged into a properly grounded wall outlet and that the power cord supplied with the unit is used and not modified 3 Ensure that the unit is always operated with the factory installed cover set on the unit 4 Make no modifications to the eq...

Page 5: ...xperienced radioltele vision technician for additional suggestions The user may find the following booklet prepared by the Federal Communications Commission to be helpful How to Identify and Resolve Radio TV Interference Problems This booklet is available from the U S Government Printing Office Washington D C 20402 Stock No 004 000 00345 4 Note The operator of a computing device may be required to...

Page 6: ...terface 2 29 2 7 2 Programming Considerations 2 29 2 8 KEYBOARD 2 38 2 8 1 Keyboard Layout and Scan Codes 2 39 2 8 2 Interface 2 41 2 9 CALENDAR AND CLOCK GENERATOR 2 42 2 9 1 Circuit Description 2 43 2 9 2 Programming Considerations 2 44 2 10 JUMPER SETTINGS 2 44 CHAPTER 3 CONTROLLER PCB 3 1 MOTHER BOARD CARD CAGE INTERFACE 3 1 3 2 CRT DISPLAY CONTROL 3 4 3 2 1 Display Buffer Memory 3 5 3 2 2 Pro...

Page 7: ...0 3 6 4 2 Synchronous Operating Mode 3 53 3 6 4 3 Business Machine Operating Mode 3 57 3 6 5 Status Word Format 3 59 3 7 SOUND CONTROL 3 60 3 7 1 Interface 3 61 3 7 2 Programming Considerations 3 62 3 8 ARITHMETIC PROCESSING UNIT 3 62 3 9 JUMPER SETTINGS 3 64 CHAPTER 4 POWER SUPPLY APPENDIX A INTEGRATED CIRCUIT DATA SHEETS Al 16 BIT MICROPROCESSOR AI I A2 PROGRAMMABLE COMMUNICATION INTERFACES A2 1...

Page 8: ...nts cont d APPENDIX C PROGRAMMABLE ARRAY LOGIC DECODING SPECIFICATIONS APPENDIX D CHARACTER CODE AND KEYBOARD INFORMATION APPENDIX E 110 PORT ADDRESSES AND INSTRUCTIONS APPENDIX F HARDWARE SPECIFICATIONS Vll ...

Page 9: ...mmand Words 2 24 2 16 Interrupt Operation Command Words 2 25 2 17 System Memory Map 2 26 2 18 Main Memory Block Diagram 2 27 2 19 Battery Backed Memory Block Diagram 2 28 2 20 Parallel Printer Control Block Diagram 2 30 2 21 Parallel Printer Cable Connections 2 32 2 22 Parallel Printer Controller Interface Timing 2 36 2 23 Parallel Printer Controller Interface at Paper Out Status 2 37 2 24 Keyboar...

Page 10: ...r Block Diagram Communications Controller Cable Connections Asynchronous Mode Instruction Word Command Instruction Word Format Communications Controller Circuit for Asynchronous Operation Synchronous Mode Instruction Word Communications Controller Circuit for Synchronous Operation Using External Clock Communications Controller Circuit for Synchronous Operation Using Internal Clock Communications C...

Page 11: ...oard Interface Lines 2 42 Clock Calendar Instruction Format 2 44 Attribute Description for Character Attribute Code 3 6 GDC I O Address and Bit Map 3 9 Contents of the GDC Status Register 3 lO GOC Symbols 3 11 GOC Commands 3 14 GDC Command Constants 3 18 Bit Description of the FDC Main Status Register 3 23 FOC Symbols 3 24 FDC Commands 3 27 FDC Status Register 0 3 33 FOC Status Register 1 3 34 FDC...

Page 12: ...Location of PAL Device C l PFBOIB Inputs Outputs C 2 PFB02B Inputs Outputs C 3 PFCOI Inputs Outputs C 4 NMS02 Inputs Outputs C 5 Code Table D 2 ASCII Special Characters D 3 APC Special Characters D 4 Quick Reference Guide for ASCII Special Character APC Spe cial Character Association D 5 I O Port Address and Instructions for the DMA Controller E 2 I O Port Addresses and Instructions for the Interr...

Page 13: ...Address and Instruction for the BBM Enable E 9 110 Port Addresses and Instructions for the APU E 9 110 Port Address and Instruction for the Power Off Control E 9 110 Port Addresses and Instructions for the Sound Control E 10 110 Port Addresses and Instructions for the Timer E 1O 110 Port Addresses and Instructions for the ODA Controller Number 1 E ll E 18 110 Port Addresses and Instructions for th...

Page 14: ...ces Chapter 2 Processor PCB includes descriptions and technical information for the devices contained on the Processor PCB along with programming considerations where appropriate Chapter 3 Controller PCB includes information similar to that in Chapter 2 for the devices contained on the Controller PCB Chapter 4 Power Supply contains detailed specifications for the system power source Appendices A t...

Page 15: ...ination DMC Direct Memory Access OCW Operational Command Cycle Word OS Data Segment ODA Output Device Adapter EPROM Erasable Programmable PAL Programmable Array Read Only Memory Logic ES Extra Segment PCB Printed Circuit Board FDC Flexible Disk Drive POF Power Off Control Controller RAM Random Access Memory FDD Flexible Disk Drive ROM Read Only Memory FIFO First In First Out rpm Revolutions Per Mi...

Page 16: ...heart ofthe APC has a CRT Display one or two 8 inch FDDs an ON OFF switch and several controls associated with the CRT Display Three Input Output I O cable connectors are available at the rear of the cabinet The CPU memory and basic control logic are contained in the Main Unit on two quad layered Printed Circuit Boards PCB a Processor PCB G9PFBU and a Controller PCB G9PFCU These PCBs plug into a m...

Page 17: ...INTER CONTROL J I 8255 KDnOARD CON IROL AUER A1E I O CONTROLLER OPTlO iALj Calendar and Clock Controller which keeps track ofthe month date day of week hour minute and second and runs on battery power when ac power is off thus preserving the time date setting The Controller PCB contains as standard equipment CRT Display Control which can generate 250 predefined characters and allows you to create ...

Page 18: ...h performance energy efficient design featuring direct drive by a dc motor Head loading and positioning is microprocessor controlled for greater accuracy and minimum wear and damage to the media surface Variable Frequency Oscillation VFO is employed to improve data transfer The APC comes equipped with a 12 inch diagonal green phosphor monochrome CRT or a 12 inch 8 color CRT Either unit has a self ...

Page 19: ...ng It also prints bidirectionally and offers word processor functions such as automatic underlining shadowing bold face printing as well as several paper handling accessories The standard APC comes equipped with 128 KB of RAM which resides on the Processor PCB With the optional memory expansion kits RAM can be expanded to 640 KB The asynchronous synchronous serial I O communications adapter is a s...

Page 20: ...0 II 0 0 0 D0 Dog CJ hn D oTM4 CJO DO DO c JO Cl OODOc J D ODODDDD ODD D D DO ODD D D 0 0 O D 0 0 S DDDDD D ODD 0 DO ODD 0 0 DO DOD 0 DOD G9PFBU vIAl MEMORY Figure 2 1 Processor PCB BATTERY POWER SLPPLY CO l lECTOR PARALLEL PRI fI lOR I ITERF CE O l lECTOR RED LED KEYBOARD INTERFACE COI I ECTOR GREEN LED 11 in As shown in Figure 2 1 three cable connectors are on the Processor PCB two are 26 pin co...

Page 21: ...l 8086 microprocessor 2 3 Capable of addressing one MB of memory Driven by an NEC pPD8284 clock generator at 4 9152 MHz A 20 bit bidirectional address bus 16 bits of which serve also as the data bus and related buffers controls and ports A DMA controller to permit high speed data transmission between input output devices without intervention of the microprocessor I U756 II Ill _ _ 5 _ 12 c 12 Cl C...

Page 22: ...tJPD1990AC which is battery protected and generates day month day of the week hour minute and second information 2 1 MOTHER BOARD CARD CAGE INTERFACE The Mother Board contains five card edge socket connectors each having 100 contacts 50 on a side see Figure 2 3 All contacts are connected as a bus to each PCB socket R50 R49 tFRONT I LSO I L49 I I I I I II LJUu Figure 2 3 Mother Board Card Cage Inte...

Page 23: ...upt controller which activates one of the IS R12 interrupt lines to the processor the interrupt request signal is maintained until acknow ledgement from the processor IRO has the highest priority and IRIS the lowest priority These lines are active Low R13 R14 DRQO to R DMA Request aThrough 3 These lines trans RlS R16 DRQ3 mit requests by 110 devices for DMA service These signals remain active unti...

Page 24: ...this line goes High every device in the system is initialized This line is activated at power on W 110 Write A Low on this line instructs the 110 device to receive data from the data bus Either the DMA controller or processor can activate the line R Ready A High on this line indicates that data has been received by an 110 device or memory or that preparation of data is com plete It is pulled Low b...

Page 25: ...ration The line is inactive High during memory refresh cycles W Memory Read This line instructs the addi tional memory to transmit its data onto the data bus Either the processor or DMA con troller can activate this signal which is active Low W Memory Refresh When this line IS Low dynamic memory is refreshed W Memory Write When Low this line instructs the selected memory to receive the data on the...

Page 26: ... line is active High the memory or 110 device associated with the least significant half of the data is enabled to read or transmit its data R31 L30 Al to A7 W Address Bits 1 Through 7 These seven lines R32 L31 address the memory or 110 device These R33 L32 signals are latched L33 R34 L34 ADO to W Address and Data Lines 0 Through 15 These R35 L35 AD15 16 lines are bidirectional and time multi R36 ...

Page 27: ... 1 30 ns IOns lIOns 10nsMIN __ 1 xAS TO A15 rDO A TrAA INN V AL ID 35ns 110ns r _ 10 ns I I I xAS TO A15 Xr D A T A O U T X 35ns H l _ _ _ _ _ _ ________ l jS5 ns NOTE WITH MEMORY IN REFRESH MW BECOMES ACTIVE BEFORE MRQ 1330 ns MIN l 2 OA I __ 1 _________________________ I c Figure 2 4 Processor Timing 2 8 ...

Page 28: ...LE _ _ I 200 ns IJOO n I 130 ns ADS TO AD15 _ X AS AI5 X IPOns I 100ns AO TO A7 x VALID X ___ I DACK I MRD IOR I 190 ns 1 I 190 ns I O ____ J MRiIOW 1 19ons I I TC Il70 n 1 I 170 ns I DMC _ _ I 2 s 1 1 s IMAX 7 Figure 2 5 DMA Timing 2 9 ...

Page 29: ...cessor PCB 2 10 PHIO lOR lOW 45 r to MIN RDY J Figure 2 6 RDY Signal Timing RFSH RFSH RAS MRQ MW NOTE THE RFSH AND RAS SIGNALS ARE GENERATED IN THE MEMORY FROM THE RFSH SIGNAL Figure 2 7 RFSH Signal Timing ...

Page 30: ... AO TO A19 IRQ lOR lOW BHE IRST PHIO LS244 AO TO A19 2 RDY vee 8284 I RDY LSTTL X111 I LOGICAL 1 3 IRO TO IRll DRQO TO DRQl Vee LS14 8259A OR 8237 5 4 DACK 8237 5 p J LSTTL Figvre 2 8 Processor Interface Circuits 2 11 ...

Page 31: ...or PCB l PHIO LS14 I o I 1 00 2 IRST Vee 30 K LS14 51 10 22 3 IRQ lOR lOW BHE DACK LS14 o I 4 _D_Y___________ _ _ _ LS OPEN COLLECTOR 5 IRO TO IRll DRQO TO DRQl LS TTL Figure 2 9 Device Interface Circuits 2 12 ...

Page 32: ...e execution unit are 16 bits wide for fast operation A 16 bit arithmetic logic unit manages the general registers and instruc tion operands and maintains status and control flags The execution unit is a strictly internal device and has no connection to the outside world All instructions and memory access operations are accomplished by the bus interface unit The bus interface unit functions as a go...

Page 33: ...ress to a physical address first shift the base address byte 4 bits to the left by multiplying it by sixteen then add the result to the offset byte 2 3 DIRECT MEMORY ACCESS Because it bypasses processor intervention DMA provides a much faster way of moving data between I O devices and memory Supported by the NEC LSI 8237 5 DMA Controller DMA employs 16 address lines and 4 bits of page addressing t...

Page 34: ...5 AI4 AI3 AI2 All AIO A9 A8 CHO DMA Count R W II W7 W6 W5 W4 W3 W2 WI WO WI5WI4WI3WI2WII WlOW9 W8 CH I DMA Address R W 03 A7 A6 AS A4 A3 A2 Al AD AI5 AI4 AI3 AI2 All AIO A9 A8 CHI DMA Count R W 13 W7 W6 W5 W4 W3 W2 WI WO WI5WI4WI3WI2WII WIOW9 W8 CH2 DMA Address R W 05 A7 A6 AS A4 A3 A2 Al AO AI5 AI4 AI3 AI2 All AIO A9 A8 CH2 DMA Count R W 15 W7 W6 W5 W4 W3 W2 WI WO WI5WI4WI3Wl2WII WIO V9 W8 CH3 DM...

Page 35: ... 0 0 0 0 A A 19 18 Read Temp Register R ID D D D D D D 7 6 5 4 3 2 Master Clear W ID COMMAND REGISTER 7 6 5 4 3 2 1 0 BIT NUMBER l J 1 I I I I I I I o MEMORY TO MEMORY DISABLE X DON T CARE I I o CONTROLLER ENABLE 1 CONTROLLER DISABLE o NORMAL TIMING o FIXED PRIORITY 1 ROTATING PRIORITY o LATE WRITE SELECTION o DREQ SENSE ACTIVE HIGH o DACK SENSE ACTIVE LOW Figure 2 10 DMA Command and Mode Register...

Page 36: ...RESS DECREMENT SELECT 00 DEMAND MODE SELECT 01 SINGLE MODE SELECT 10 BLOCK MODE SELECT 11 CASCADE MODE SELECT Figure 2 10 DMA Command and Mode Registers cont d REQUEST REGISTER 7 6 5 4 3 2 o BIT NUMBER V _ J L y J L 10 11 DON T CARE SELECT CHANNEL 0 SELECT CHANNEL 1 SELECT CHANNEL 2 SELECT CHANNEL 3 RESET REQUEST BIT SET REQUEST BIT SOFTWARE REQUESTS WILL BE SERVICED ONLY IF THE CHANNEL IS IN BLOC...

Page 37: ...ETS OR CLEARS THE MASK BITS IS SIMILAR IN FORM TO THAT USED WITH THE REQUEST REGISTER 7 6 5 4 3 2 o BIT NUMBER I I I I I I L L _ _ _ L _ _ _ _ CLEAR CHANNEL 0 MASK BIT SET CHANNEL 0 MASK BIT CLEAR CHANNEL 1 MASK BIT SET CHANNEL 1 MASK BIT CLEAR CHANNEL 2 MASK BIT SET CHANNEL 2 MASK BIT CLEAR CHANNEL 3 MASK BIT SET CHANNEL 3 MASK BIT ALL FOUR BITS OF THE MASK REGISTER MAY ALSO BE WRITTEN WITH A SIN...

Page 38: ...S APPLIED THESE BITS ARE CLEARED UPON RESET AND ON EACH STATUS READ Figure 2 12 DMA Status Register 2 4 INTERVAL TIMER The NEC J1PD8253 5 Programmable Interval Timer has three timer counter out puts ChannelO is attached to interrupt request Channel 3 Channell is sent to the synchronous asynchronous communications controller on the Controller PCB see Chapter 3 Channel 2 is not used Figure 2 13 is a...

Page 39: ...s IR7 through IRI4 These 15 available interrupt lines are assigned to service specific devices in order of priority Table 2 4 lists the interrupt lines There are two interactions between the processor and the interrupt controller The first is the acknowledgement process during which the processor transmits acknowledgement of the interrupt request to the interrupt controller During the second proce...

Page 40: ... Not used IR3 Timer IR4 Keyboard IR5 Not used IR6 Not used Slave IR7 Printer IR8 Not used IR9 Not used IRlO CRT IRil FDD IRI2 Not used IRI3 Not used IRI4 APU Processor PCB TO THE PROCESSOR INTERRUPT VECTOR BYTE T7 T6 T5 T4 T3 a a a T7 T6 T5 T4 T3 a a I T7 T6 T5 T4 T3 a I a T7 T6 T5 T4 T3 a I I T7 T6 T5 T4 T3 I a a T7 T6 T5 T4 T3 I a I T7 T6 T5 T4 T3 I I a T7 T6 T5 T4 T3 a a a T7 T6 T5 T4 T3 a 0 I ...

Page 41: ... W 22 0 0 0 0 0 0 0 I OCW I W 22 M6 M5 M4 M3 M2 MI MO OCW2 W 20 R S E 0 0 L2 Ll LO L 0 I OCW3 W 20 0 E S 0 I P P R S M R I M M S Poll Mode R 20 I W2 WI WO Read IRR R 20 I I I I I I I R R R R R R R 6 5 4 3 2 I 0 Read ISR R 20 I I I I I I I S S S S S S S 6 5 4 3 2 I 0 Read Mask R 22 M6 M5 M4 M3 M2 MI MO Slave ICW I W 28 0 0 0 I 0 0 0 I ICW2 W 2A T7 T6 T5 T4 T3 0 0 0 ICW 3 W 2A 0 0 0 0 0 I I I ICW4 W...

Page 42: ...6 5 4 3 2 1 0 OCW 1 W 2A MI4 M13 M12 MIl MIO M9 M8 M7 OCW2 W 28 R S E 0 0 L2 L1 LO L 0 I OCW3 W 28 0 E S 0 1 P R R S M R I M M S Poll Mode R 28 I W2 WI WO Read IRR IR IR IR IR IR IR IR IR R 28 14 13 12 11 lO 9 8 7 Read IRR IS IS IS IS IS IS IS IS R 28 14 13 12 11 lO 9 8 7 Read Mask R 2A M14 M13 M12 MIl M10 M9 M8 M7 2 23 ...

Page 43: ... 1s71 s61 SSI S41 s31 s21 SI 1SO I fL fL Jt f t t Lt Lf________ l IR INPUT HAS A SLAVE 0 IR INPUT DOES NOT HAVE A SLAVE ICW3 SLAVE SO TO S6 0 S7 1 102 101 100 tL _ t l t____ SLAVE ID SET ALL TO I ICW4 I 0 I 0 I 0 I SFNM I BUF MIS I AEOII tJPM I 1 8086 8088 MODE 0 MCS 80 8S MODE 1 AUTO EOI L O NORMALEOI BUF MIS L ________________ 0 X NON BUFFERED MODE 1 0 BUFFERED MODE SLAVE 1 1 BUFFER MODE MASTER ...

Page 44: ...NSPECIFIC EO COMMAND SPECIFIC EO COMMAND SLAVE IR7 IR8 IR9 IRIO IRll IR12 IRI3 IRI4 ROTATE ON NONSPECIFIC EO COMMAND ROTATE IN AUTOMATIC EO MODE SET ROTATE IN AUTOMATIC EO MODE CLEAR ROTATE ON SPECIFIC EO COMMAND SET PRIORITY COMMAND NO OPERATION DO RR RIS o READ IRR READISR I POLL COMMAND 0 NO POLL COMMAND ESMM SMM o RESET SPECIAL MASK SET SPECIAL MASK Figure 2 16 Interrupt Operation Command Word...

Page 45: ...000 20000 AOOOO AI000 COOOO DOOOO EOOOO FOOOO FEOOO FFFFF STANDARD RAM EXPANDED RAM 4KBBM DUPLICATE BBM ADDRESSES ALPHANUMERIC ROM NOT USED SPECIAL CHARACTERS RAM ROM DUPLICATE ADDRESSES 8KROM Figure 2 17 System Memory Map 11 128 KB 128 KB MAIN MEMORY 640 KB USER RAM BATTERY BACKED MEMORY 4 KB REPEATED 32 TIMES DISPLAY MEMORY ...

Page 46: ...ed parity error lights the D4 red Light Emitting Diode LED located near the top edge of the Processor PCB As shown in Figure 2 17 the main memory is expandable to a maximum of640 KB of which 256 KB can be supported by the present APC equipment configuration ADDRESSES 1 TO 16 REFRESH ADDRESS CLOCK MRQ MW AO BHE REFRESH ADDRESS CONNECTOR t REFRESH TIMER REFRESH REQUEST REFRESH ARBITER Figure 2 18 Ma...

Page 47: ...mation and is protected from loss for at least two years by the battery that plugs into the Processor PCB As shown in Figure 2 19 the BBM read write operation is identical to that of the main memory except for a BBM write protect circuit that safeguards the BBM from unintentional data manipulation HIGH D8 TO DIS DATA BUS _ _ _ _ _ _ _ _ _ _ _ _ _ J f______ BBM F F COMMAND MW 5 Vde BATTERY ADDRESS ...

Page 48: ...e parallel printer control consists of an NEC pPD8255A Programmable Peripheral Controller that interfaces with connector CN2 through LS244 drivers A flat type 26 conductor cable connects the CN2 board connector to a connector at the rear ofthe main unit that in turn goes to the printer The pin connections are listed in Table 2 6 The interface is adaptable to either an Output Device Adapter ODA or ...

Page 49: ... I DRIVER PB7 PAO PA3 PA4 PA7 DRIVER PC7 I PC2 PC t rl SHIFT PAl PC2 1 PC4 I Figure 2 20 Parallel Printer Control Block Diagram 2 30 DATA 8 TO CONNECTOR I L PBO TO PB7 PE PRINTER CABLE CONNECTOR PIN NUMBERS 11 13 15 17 19 21 23 25 22 SELECT 7 FAULT 14 5V 18 INPUT PRIME 10 B ST USY 3 ROBE SG 5 1 9 20 4 12 24 6 16 26 ...

Page 50: ...Ground 14 NC NC NC 15 NC NC Signal Ground 16 NC NC Chassis Ground 17 NC NC 5 Vdc 18 27 NC24 Twisted Pair Ground Pin 1 19 NC NC Ground Pin 2 20 20 8 Ground Pin 3 21 21 21 Ground Pin 4 22 5 3 Ground Pin 5 23 24 10 Ground Pin 6 24 26 11 Ground Pin 7 25 28 12 Ground Pin 8 26 30 13 Ground Pin 9 27 31 26 Ground Pin 10 28 NC Ground Pin 11 29 NC Ground Pin 31 30 NC Input Prime 31 23 22 FaUIT 32 25 23 Sign...

Page 51: ...Ii 7 Z1117772 C 26 24 6 4 2 G9PFBU PCB 36 18 B 19 1 36 18 A PINS 14 TO 18 AND 32 TO 36 HAVE NO CONNECTION MOUNTED ON THE REAR PANEL MARKED PTR I 0 n 4 Y REAR PANEL PRINTER CABLE CONNECTOR RIBBON TYPE INTERCONECTING CABLE NOTE SEE TABLE 2 6 FOR PIN NUMBERS AT LOCATIONS A B AND C Figure 2 21 Parallel Printer Cable Connect ...

Page 52: ... 2 During printing operation 3 In offline state 4 During printer error status STROBE APC Strobe pulse to read data in The signal level is normally High Read in of data is performed at the Low level of this signal SG Twisted pair return signal ground level SELECT Printer Goes high to indicate that the printer is in selected state ACKNLG Printer Acknowledge goes Low to indicate that data has been re...

Page 53: ...TA 1 APC Data lines from 8255A PBO through PB7 High is logic 1 Low is logic O DATA 2 APC DATA 3 APC DATA 4 APC DATA 5 APC DATA 6 APC DATA 7 APC DATA 8 APC FAULT Printer Goes Low when the printer is in 1 Paper End state 2 Offline state 3 Error state 5 V Printer Device Control DCN PE Printer Goes high to indicate that printer is out of paper 2 34 ...

Page 54: ...ite Signal 1 W 6E 0 0 0 0 0 I 0 N T E R Write Signal 2 W 6E 0 0 0 0 0 1 I M S M Write Signal 3 W 6E 0 0 0 0 1 0 0 A S K Write Signal 4 W 6E 0 0 0 0 I 1 I I R T M Write Signal 5 W 6C I X X A X X X X P S K S F E R A L D P Read Signal R 68 5 0 0 U E 0 R E V L C Q T T D D D D D D D D A A A A A A A A Write Data W 6A T T T T T T T T A A A A A A A A 8 7 6 5 4 3 2 I 2 35 ...

Page 55: ...STB BUSY LOW INPUT BUSY ACK I I I T4 DESCRIPTION Set the 8255 Mode Interrupt Enable Flag lNTE Receive Machine Set RMS Mask Set or Reset 1 Reset 0 Set Input Prime lP Set or Reset IP and Mask Set or Reset Read the status of the printer Write data to be printed TS I I I I I I T6 T4 1 Flag On 0 Flag Off 1 RMS On 0 RMS Off 1 Reset 0 Set Tl TO T3 1 iJ s MIN T4 100 ns MAX TS 0 1 TO 0 5 ms T6 6 TO 8 iJ S ...

Page 56: ...ming cont d NO DATA IS IN THE DATA BUFFER PE SELECT FAULT BUSY __ s SEL SW ON RECEIVE DATA PRINT ONE LINE STORED DATA IS IN THE DATA BUFFER PE OCCURS PE SELECT FAULT BUSY ________________ PE DESELECT FAULT BUSY PRINT ONE LINE r J L _ _ _ _ __ Figure 2 23 Parallel Printer Controller Interface at Paper Out Status Processor PCB 2 37 ...

Page 57: ... positions The 8048 microprocessor in combination with an LS74159 decoder chip produces a scan code output function peculiar to each key position and shift control status These scan codes are sent to the Processor PCB on an eight bit scan data bus designated SDI through SD8 8 X 16 KEY MATRIX Pressing a key produces a strobe that latches the corresponding scan code into a key data register or switc...

Page 58: ...S IN PARENTHESES DESIGNATE KEY POSITION DNONLOCKABLE SWITCH KEYS DLOCKABLE SWITCH KEYS Figure 2 25 Keyboard Layout Table 2 10 Keyboard Scan Codes KEY SCAN KEY SCAN KEY POSITION CODE POSITION CODE POSITION 1 38 9C 75 2 80 39 98 76 3 81 40 51 77 4 82 41 57 78 5 83 42 45 79 6 84 43 52 80 7 85 44 54 81 8 86 45 59 82 INS S5 S6 DEL 90 91 t 96 101 102 107 SCAN CODE 4D 2C 2E 2F 20 Positions 1 FNC 54 CTRL ...

Page 59: ... 92 77 19 91 56 41 93 78 20 92 57 53 94 79 21 93 58 44 95 6D 22 94 59 46 96 F7 23 95 60 47 97 74 24 IB 61 48 98 75 25 31 62 4A 99 76 26 32 63 4B 100 6B 27 33 64 4C 101 FA 28 34 65 3A 102 F9 29 35 66 3B 103 71 30 36 67 97 104 72 31 37 68 105 73 32 38 69 5A 106 FD 33 39 70 58 107 F8 34 30 71 43 108 70 35 50 72 56 109 6E 36 2D 73 42 37 40 74 4E Positions 1 FNC 54 CTRL 55 CAPS LOCK 68 and 79 SHIFT 80 ...

Page 60: ... of the Main Unit see Figure 2 26 and Table 2 11 The cable is a shielded 19 wire design that includes power 5 Vdc grounds and twelve signal lines The cable is permanently attached to the Keyboard Figure 2 26 Keyboard Interface 1 3 23 25 1000 0001 000 1 0 C 2 4 24 26 Processor PCB 2 41 ...

Page 61: ...bug 20 Signal Ground 21 Signal Ground 22 Signal Ground 23 5 Vdc 24 5 Vdc 25 Not used 26 Not used 2 9 CALENDAR AND CLOCK GENERATOR The Calendar and Clock Generator is supported by a CMOS Integrated Circuit IC NEC JlPDI990AC This IC independently registers the month day of the month day of the week hour minute and second and it can receive or send this information from or to the microprocessor Becau...

Page 62: ...er prevents calendar and clock data loss A 14 pin IC encloses all functions 74LS174 ADO TO 6 BIT v LATCH AD7 A CS r CONTROL I LOGIC 5 v VDD SUPPLY b CIRCUIT J BATTERY BATTERY VOLTAGE CHECKER 74LS367 Jo I Figure 2 27 Clock Calendar Block Diagram 1PDl990A co TO XL 1 II C2 STB Cl T XL It CLK 32 768 kHz Dl DO CS DE VDD G I 7 7 VDD LED GREEN 5V J Processor PCB 2 43 ...

Page 63: ... bits 4 bits 8 bits 8 bits 8 bits 8 bits month day of wk date hour minute second The writelread instruction format is shown in Table 2 12 and Figure 2 28 Table 2 12 Clock Calendar Instruction Format READ I O DATA BUS DESCRIPTION INSTRUCTION WRITE ADDRESS 7 6 5 4 3 2 0 D C S Set Register W 58 0 0 L T C2 CI CO See Figure I K B 2 28 1 B Read Data R 58 A D See Figure T 0 2 28 2 T ...

Page 64: ...EAD COMMAND I 0 0 ILLEGAL o I ILLEGAL I 0 ILLEGAL I I ILU AL L _ _ _ _ _ STROBE COMMANDS 2 CI CO ARE INDEPENDENTLY LATCHED BY TIlE STB INPUT CLOCK DATA INPUT OUTPUT IN SYNCHRONIZATION WITH CLK INPUT DATA INPUT 2 READ DATA DATA OUTPLT BATTERY VOLTM E CIIECK 0 NORMAL ELECTRO CHEM 3 OV SANYO 2 W I LOW ELECTRO CIlEM 3 0V SANYO 2 3V Figure 2 28 Clock Calendar Format Processor PCB 2 45 ...

Page 65: ...ce for a Centronics type or aDA printer set TM2 TM3 and TM4 as instructed in Figure 2 29 CJ FS2s9l Dog M C CJ 0 eN CJD 0 c F ODD 000 2 c J U c J c J D CJ D c J DO c J 0 Q J Doo DO D D D c JD c J 0 DOD c J 0000000 DDDDDDCJ c JODDDOCJ c J2 D g CJ c J DODOO D c JD 0 0 0 Cl c JCl 0 0 0 Cl 0 OODDDClO G9PFBU Figure 2 29 Processor PCB Jumper Settings FOR CENTRONICS TYPE PRINTER INTERFACE TM2 J TM3 Q m SH...

Page 66: ...rol for the 12 inch monochrome or color display designed around the PD7220 graphic display controller An 8 inch FDD control that can read from and drive double sided double density flexible disks or single sided single density disks Serial 110 device control supported by the NEC 8251A controller converts serial data to parallel data and parallel data to serial data it can do so synchronously or as...

Page 67: ... 0 0 D D 1 1 6116 D 1 0 I I ID GJo I D D D D D 0 D D I COMMCNICAT10N LSI I 1 TM3 1 0 0 DD COMMliNICAT10N INTERFACE CONNECTOR CRT UNIT INTERFACE CONNECTOR FDD CONTROL CLOCK FDD INTERFACE CONNECTOR SPEAKER INTERFACE CONNECTOR VOLUME INTERFACE CONNECTOR CRT CONTROL LSI SOllND LSI FDD CONTROLLER Figure 3 1 Controller PCB 3 2 ...

Page 68: ...ONTROL 8231 ARITHMETIC PROCESSING UNIT 1771 006 SOUNO CONTROL Figure 3 2 Controller PCB Block Diagram OSl TO 4 LWC D1R FLR STP WOT HOL SSL MFM WGT VSYN ROY PRT TSO FUS TKO IDX ROT WID SD SD RS ER STI RD CS DR RT ST2 O CI INT 14 3VOLUME Controller PCB 3 3 ...

Page 69: ...haracters A 26th line reserved for system status information Direct drive output An 8 dot by 19 dot character box A 7 dot by II dot character 8 dot by 16 dot special programmable characters A character generator supplies the video process logic with the information neces sary for displaying the characters Additionally a special character generator contains the fonts for user programmable character...

Page 70: ...f data indicate the character code or special character code for an individual display position A l in the character set bit Bit 7 indicates that the character comes from the special or user programmed character set see Figure 3 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 I0 I0 I0 I0 0 I0 I I y L CHARACTER SET BIT CHARACTER CODE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 I0 I0 I0 I0 I0 0 I0 I L CHAR...

Page 71: ...are shown in Table 3 1 and Figure 3 5 Table 3 1 Attribute Description for Character Attribute Code ATTRIBUTE FUNCTION COMMENT GR Green Must always equal 1 with monochrome display BU Blue Character is blue R H Redl Red color color display high highlight lighted character monochrome RV Reverse Character and Field Video video transposed BL Blinking VB Vertical bar OB Over bar UB Under bar GR R H Null...

Page 72: ...s and 1 for the attribute code address For example character code address 0000 is associated with attribute code address 1000 because their addresses are identical except for Bit 12 Figure 3 6 is a memory map that shows the organization of the display buffer memory Notice that Bit 12 determines whether an address accesses a character code Bit 12 0 or a character attribute code Bit 12 1 ADDRESS BUS...

Page 73: ...isplay Position and Video Screen 3 2 2 Programming Considerations The G DC has four registers all of which can be accessed directly or indirectly by the 8086 processor status register First In First Out FIFO command register and data register The I O addresses functions and bit maps are summarized in Table 3 2 The status register is an 8 bit read only register Its I O address is 80 HEX Using the 8...

Page 74: ...rite C C C C C 7 6 5 4 3 46 Write BIT 7 6 5 4 3 Figure 3 8 GDC Status Register Bit Map 2 I 0 F F D E F R P P P 2 1 0 D D D 2 I 0 C C C 2 I 0 C R T 2 INSTRUCTION Read Status Register Write Parameter Register Read Data Register Write Command Register Reset Interrupt Request 1 0 DATA READY FIFO BUFFER FULL FIFO BUFFER EMPTY DRAWING DMA EXECUTE VERTICAL SYNC HORIZONTAL BLANK NOT USED 3 9 ...

Page 75: ...ent to the GDC have been processed 3 While the GDC is drawing a graphics figure this status bit is a I 4 This bit is a 1 during DMA data transfers 5 Vertical retrace sync occurs while this flag is a I The vertical sync flag coordinates display format modifying commands to the blanked interval surrounding vertical sync This eliminates display disturbances 6 A 1 value for this flag signifies that ho...

Page 76: ...5 BLD Blinking Disable Cursor blinks BLD 0 or does not blink BLD 1 BL Blinking Rate Controls frequency of blinking CFl Cursor Finish Controls at which line the cursor finishes CHR Character Mode Character Mode CHR and Graphic Mode G define the display modes as follows CHR G Mode 0 0 Character Mode 0 1 0 Character Mode 1 0 1 Not Used CIR Circle Indicates that a circle is being drawn if CIR 1 CSR Di...

Page 77: ...HR HBP Horizontal Defines the amount of left horizontal Back Porch blanking time HFP Horizontal Defines the amount of right horizontal Front Porch blanking time HOS Horizontal Sync Horizontal sync occurs when HOS 1 I Interlace Display is interlaced I 1 or not inter laced I 0 LIN Line LIN 1 indicates that line is being drawn L F Lines Per Frame Defines the number of lines in the vertical display pe...

Page 78: ...roll address REC Rectangle REC 1 indicates that a rectangle is being drawn S Shrink Affects line center S 1 SLO to SL9 Scroll Line Controls scroll line count SLA Slant Controls slant of text or drawing VBP Vertical Defines the amount of upper vertical Back Porch blanking time VES Vertical Sync Vertical sync occurs when VES 1 VFP Vertical Defines the amount of lower vertical Front Porch blanking ti...

Page 79: ...video synchronization mode RESET Resets the GOC to its C 0 0 0 0 0 0 0 0 idle state and specifies video display format DISP START Starts the display C 0 1 1 0 1 0 1 1 scanning process DISP START C 0 0 0 0 1 I 0 J DISP STOP Stops the display C 0 0 0 0 1 1 0 0 scanning process ZOOMW Specifies zoom coeffi C 0 1 0 0 0 1 I 0 cients for the display P ZR ZW and graphics character writing CSRW Sets the po...

Page 80: ...and specifies the P4 0 1M SL9 SL8 SL7 SL6 SLS SL4 eight bytes for the P5 A7 A6 A5 A4 A3 A2 Al AO graphics character P6 AI5 AI4 AI3 AI2 All AIO A9 A8 P7 SL3 SL2 SLi SLO 0 0 0 0 P8 0 1M SL9 SL8 SL7 SL6 SL5 SL4 CODEW Writes the character C 0 0 I 0 0 0 MOr code data into the PI C7 C6 C5 C4 C3 C2 CI CO display memory P2 CI5 CI4 CI3 CI2 CII CIO C9 C8 LOW BYTE CODEW Writes the low order C 0 0 I I 0 0 MOD...

Page 81: ... set specifies the PI SL R C T L DIR parameters for the P2 DC7 DC6 DC5 DC4 DC3 DC2 DCl DCO drawing processor P3 DGD DCI3 DCI2 DCII DCIO DC9 DC8 P4 D7 D6 D5 D4 D3 D2 DI DO P5 DI3 DI2 Dli DIO D9 D8 P6 D27 D26 D25 D24 D23 D22 D2I D20 P7 D213 D212 D2II D210 D29 D28 P8 DI7 DI6 DI5 DI4 DI3 DI2 DII DIO P9 DII3 DI12 DIll DIIO Dl9 DI8 PIO DM7 DM6 DM5 DM4 DM3 DM2 DMI DMO PI I DMI3 DMI2 DMII DMIO DM9 DM8 WOR...

Page 82: ...MA C a a I a a I MOD write transfer for the entire word LOW BYTE DREQW Requests a DMA C a a I I a I MOD write transfer for the low order byte only HIGH BYTE DREQW Requests a DMA C a a I I I I MOD write transfer for the high order byte only WORD DREQR Requests a DMA C I a I a a I MOD read transfer for the entire word LOW BYTE DREQR Requests a DMA C I 0 I I a I MOD read transfer for the low order by...

Page 83: ...Master slave Master versus slave video synchronization C ZOOMW Zooming disabled PI 00 C CSR DISP Blinking block cursor PI 12 P2 CI P3 8B C PITCH W 80 characters per row PI 50 C MASKW PI FF P2 FF 3 3 CRT DISPLAY UNIT The CRT Display unit consists ofa chassis mounted circuit a 12 inch monochrome or color CRT Display Controller PCB and internal power unit The monochrome or color display units connect...

Page 84: ...ONTROL CRT DISPLAY UNIT INTERNAL POWER SUPPLY BRIGHTNESS ADJUSTMENT GROUND A 1 1 B 2 MONOCHROME r C 3 CRT DISPLAY D 4 UNIT _ GROUND E 5 HORIZONTAL DRIVE F 6 NOT USED 7 VIDEO J 8 VERTICAL DRIVE K 9 GROUND L 10 Figure 3 9 Monochrome CRT Display Interface Controller PCB 3 19 ...

Page 85: ...TICAL DRIVE 19 VIDEO BLUE 20 GROUND Figure 3 10 Color CRT Display Interface COLOR CRT DISPLAY UNIT INTERNAL POWER SUPPLY 1 3 5 7 9 10 11 4 6 8 12 COLOR 13 CRT 14 15 DISPLAY UNIT 16 17 18 19 20 Another internal cable the power supply cable carries 115 Vac power from the system power supply to the internal power supply oftn CRT Display This internal power unit provides the CRT Display with 12 Vdc ...

Page 86: ...CONTROLLER The APC has space and power for two 8 inch FDDs The drives are soft sectored and two sided with 77 cylinders 0 to 76 They use Modified Frequency Modula tion MFM coded in 256 byte sectors except index track giving an unformatted capacity of about 1 2 MB per drive They have a track access time of 5 ms The 8 inch Flexible Disk Drive Controller FDC on the Controller PCB attaches to the FDD ...

Page 87: ... multibyte interchange of information between the FDC and the processor each command can be considered in three phases Command Phase The FDC receives all information required to perform a particular operation from the processor Execution Phase The FDC performs the operation Result Phase Status and other housekeeping information are made available to the processor ICLOCK I I WRITE I TIMING J PRECOM...

Page 88: ...DB5 Non DMA NDM The FDC is in the Non DMA Mode Mode DB6 Data Input DIO Indicates direction of data transfer Output between the FDC and the proces sor DIO 1 indicates transfer is from FDC data register to the processor DIO 0 indicates transfer is from processor to FOC data register DB7 Request for RQM Indicates Data Register is ready to Master send or receive data to or from the processor Both bits...

Page 89: ...ns ofthe command status registers Table 3 14 lists the 110 addresses and functions of the FDC registers Table 3 8 FDC Symbols SYMBOL NAME DESCRIPTION AO Address Line 0 Controls the selection of the Main Status Register AO O or Data Register AO l C Cylinder Number Specifies the selected cylinder number D Data Specifies the data pattern that is going to be written into a sector D7 to DO Data Bus 8 b...

Page 90: ... occurred 0 to 240 ms in 16 ms increments MF FM or MFM Mode If MF is Low FM Mode is selected if High MFM Mode is selected only if MFM is implemented MT Multi Track If MT is High a multitrack operation is to be performed A cylinder under both HDO and HDI is read or written N Number Specifies the number of data bytes writ ten in a sector NCN New Cylinder New cylinder number which is going to Number ...

Page 91: ...tus 1 store the status information after a ST 2 Status 2 command has been executed This ST 3 Status 3 information is available during the result phase after command execution These registers should not be confused with the main status register selected by AO 0 ST 0 to 3 can be read only after a command has been executed They contain information relevant to that particular command STP Scan Test Dur...

Page 92: ...ystem Result R STO Status information after R STI Command execution R ST2 R C Sector ID information R H after Command R R execution R N READ DELETED DATA Command W MT MF SK 0 I I 0 0 Command Codes W X X X X X HD USI usa W C Sector ID information W H prior to Command W R execution W N W EOT W GPL W DTL Execution Data transfer between the FDD and main system Result R STO Status information after R S...

Page 93: ...nd FDD Result R STO Status information after R STI command execution R ST2 R C Sector ID information R H after command R R execution R N WRITE DELETED DATA Command W MT MF 0 0 I 0 0 I Command Codes W X X X X X HD USI usa W C Sector ID information W H prior to command W R execution W N W EOT W GPL W DTL Execution Data transfer between FDD and main system Result R STO Status ID information R STI aft...

Page 94: ...d main system FDD reads all of cylinders contents from index hole to EOT Result R STO Status information after R STI command execution R ST2 R C Sector ID information R H after command R R execution R N READ ID Command W 0 MF 0 0 I 0 I 0 Command Codes W X X X X X HD USI usa Execution The first correct ID information on the cylinder is stored in data register Result R STO Status information after R...

Page 95: ...ylinder Result R STO Status information after R ST command execution R ST2 R C In this case the ID R H information has no R R meaning R N SCAN EQUAL Command W MT MF SK 0 0 0 Command Codes W X X X X X HD US usa W C Sector ID information W H prior to command W R execution W N W EOT W GPL W STP Execution Data compared between the FDD and main system Result R STO Status information after R STI command...

Page 96: ...d main system Result R STO Status information after R STI command execution R ST2 R C Sector ID information R H after command R R execution R N SCAN HIGH OR EQUAL Command W MT MF SK 1 1 1 0 1 Command Codes W X X X X X HD USI usa w C Sector ID information W H prior to command W R execution W N W EOT W GPL W STP Execution Data compared between the FDD and main system Result R STO Status information ...

Page 97: ...CN about the FDD at the end of seek operation SPECIFY Command W 0 0 0 0 0 0 I I Command Codes W SRT HUT W HLT NO No Re ult Phase SENSE DRIVE STATUS Command W 0 0 0 0 0 1 0 0 Command Codes W X X X X X HD USI usa Result R ST3 Status information about FDD SEEK Command W 0 0 0 0 1 I I 1 Command Codes W X X X X X HD USI usa W NCN Execution Head is positioned over proper cylinder on diskette No Result P...

Page 98: ...nal from FOO changed state 05 Seek End SE When the FDC completes the Seek command this flag is set to 1 High D4 Equipment EC If a fault signal is received from the Check FDD or if the track 0 signal fails to occur after 77 step pulses recalibrate command then this flag is set D3 Not Ready NR When the FDD is in the not ready state and a read or write command is issued this flag is set If a read or ...

Page 99: ...o Data ND During execution of a Read Data Write Deleted Data or Scan com mand if the FDC cannot find the sector specified in the ID register this flag is set During execution of the Read ID command if the FDC cannot read the ID field without an error then this flag is set During the execution of the Read a Cylinder command if the starting sector cannot be found then this flag is set Dl Not NW Duri...

Page 100: ...om that stored in the 10 Register this flag is set 03 Scan Equal Hit SH During execution of the Scan command if the condition of equal is satisfied this flag is set 02 Scan Not SN During execution of the Scan Satisfied command if the FDC cannot find a sector on the cylinder that meets the condition then this flag is set 01 Bad Cylinder BC This bit is related with the NO bit and when the contents o...

Page 101: ... the status of the Track osignal from the FDD 03 Two Side TS Indicates the status of the Two Side signal from the FDD 02 Head Address HD Indicates the status of Side Select signal to the FDD 01 Unit Select 1 USI Indicates the status of the Unit Select 1 signal to the FDD DO Unit Select 0 usa Indicates the status of the Unit Select 0 signal to the FDD Table 3 14 FDC Register I O Addresses and Funct...

Page 102: ...or out according to the direction line signal for each pulse present on this line Direction 7406 For each recognized pulse of the step line the read write head moves one cylinder toward the spindle if this line is active and away from the spin dle if this line is inactive Write Data 7406 For each inactive to active transition of this line while Write Enable is active the selected drive causes a fl...

Page 103: ...ctivates this line when a write pro tected diskette is mounted in the drive Track 0 The selected drive activates this line when the read write head is over Track O Read Data The selected drive supplies a pulse on this line for each flux change encountered on the disk it relays data from the flexible disk Ready This line becomes active when the selected drive is ready Dual Side When a dual sided di...

Page 104: ...ply To enable disk reading insert a disk and close the front latch this causes the drive hub to clamp the disk and turn it at 360 rpm When an index sensor detects the index hole it activates a signal The stepper motor positions the read write heads over the desired tracks for reading 3 5 1 Specifications The FDD specifications are listed in Table 3 17 Table 3 17 FDD Specifications CHARACTERISTIC S...

Page 105: ...0 mm 12 73 in 323 0 mm 7 7 Ib 3 5 Ib 20 to 80 24 Vdc IO 0 75 A starting 0 90 A average 5 Vdc 5 0 8 A 5 Vdc 5 0 07A 28 W maximum I per 109 I per 1012 I per 106 Figure 3 13 shows the signal connector interface and pin assignments Figure 3 14 illustrates the power connector interface and pin assignments 3 5 3 Terminations and Jumper Settings The location and installation of the termination resistor m...

Page 106: ...41 TWO SIDED 37 SIDE SELECT 33 HEAD LOAD 31 INDEX 29 READY 27 VFO SYNC 25 DRIVE SELECT A 23 DRIVE SELECT B 21 DRIVE SELECT C 19 DRIVE SELECT D 17 DIRECTION SELECT 15 STEP 13 WRITE DATA II WRITE GATE 9 TRACK 00 7 WRITE PROTECT 5 READ DATA 3 MFM 1 WINDOW 2 50 EVEN GROUND Figure 3 13 FDD Signal Connector Interface and Pin Assignments Controller PCB FDD CONTROL 3 41 ...

Page 107: ... LEVELS r 7 PIN I _ 13 POWER CONNECTOR 8 in FDD Figure 3 14 FDD Power Connector Interface and Pin Assignments o 0 D 0 t t TERMINATION RESISTOR MODULE 15000 661 3 R150 Figure 3 15 FDD Termination Resistor Modules Location and Installation 1 DC 24 V 2 GND 3 DC S V 4 GND S DC S V 6 GND 7 FG POWER UNIT ...

Page 108: ... 110 Communications Controller 3 6 2 Circuit Description A functional block diagram of the serial 110 device is shown in Figure 3 17 Table 3 19 lists the serial 110 commands 3 6 3 Interface The serial 110 connects to the APC rear panel with a 26 pin cable connector designated CN3 on the Controller PCB The other end of the 26 pin cable connects to a 36 pin D type connector similar to the printer co...

Page 109: ...aracteristics Specifications Processor NEC 8251A Channel 1 Transmission Mode Half Duplex or Full Duplex Synchronization Synchronous or Asynchronous Interface EIA RS 232C Line Speed Asynchronous Mode 50 to 19 2K Baud Synchronous Mode 50 to 19 2K Baud Business Machine 1200 Baud 3 44 ...

Page 110: ... RD C D TXE CS RST TXD RXD CTS RTS DSR RXC DTR TXC CLOCK GENERATOR CLKO BUSINESS MACHINE CLOCK GENERATOR cp TRANSMIT DATA SD Xl RS ER DR CS RECEIVE DATA J RD RT 1 ST2 STI Figure 3 17 Serial 1 0 Communications Controller Block Diagram Controller PCB 3 45 ...

Page 111: ... S S S S S Write Data 30 W D D D D D D D D 7 6 5 4 3 2 1 0 D S F 0 P T R T Read Status 32 R Y R R R N E E E E D D Y Y E P Write Mode A 32 W S2 S P E L2 L B2 B N S E P Write Mode S 32 W C S E E L2 L 0 0 S D P N E I R R S R E T Write Command 32 W H R S S B E R E T R N N Tx Rx Tx Write Mask 34 W E R R C C C Read Signal 34 R S I D T Write Signal 36 W D C 3 46 ...

Page 112: ...Frame Ground 1 1 1 SO 2 2 3 RD 3 3 5 RS 4 4 7 CS 5 5 9 DR 6 6 11 Signal Ground 7 7 13 CD 8 8 15 9 9 17 No signal 10 10 19 11 11 21 12 12 23 13 13 25 14 19 2 ST2 15 20 4 16 21 6 No signal RT 17 22 8 18 23 10 19 24 12 No signal ER 20 25 14 21 26 16 22 27 18 No signal 23 28 20 STI 24 29 22 25 30 24 No signal 3 47 ...

Page 113: ...dy SG ST2 TxC Modem Transmit Clock RT Modem Receive Clock ER Controller Data Terminal Ready STl RxC Controller Transmit Clock The processor can also read a status word from the 8251 A or write sync characters in the Synchronous Mode or specify that the data bus is to be read from or written to and transmitted to or received from respectively the modem Instruction to the 8251A is determined by the ...

Page 114: ... III 2 II II I i I Z Z Z I I I I C 26 24 6 4 2 G9PFCU PCB B A 36 19 19 25 2 1 14 PINS 14 TO 18 AND 32 TO 36 HAVE NO CONNECTION MOUNTED ON THE REAR PANEL MARKED COMM G9PFCU u uif G CN3 COMMUNICATIONS CABLE INTERCONNECTING CABLE Figure 3 18 Communications Controller Cable Connections 3 49 ...

Page 115: ... written in or that a status word read out A Low means that data is being written in or read out APC AB line RD READ A Low on this line indicates that the data or a status word is being read from the 8251 A APC lOR line RST RESET A High on this line places the 8251A in an idle mode wait ing for a new set of control words APC RST line 3 6 4 1 ASYNCHRONOUS OPERATING MODE The mode instruction word fo...

Page 116: ...R X E I DTR IT X EN I I Figure 3 20 Command Instruction Word Format TRANSMIT ENABLE I ENABLE o DISABLE DATA TERMI AL READY HIGH WILL FORCE DTR OUTPUT LOW RECEIVE ENABLE I ENABLE o DISABLE SEND BREAK CHARACTER I FORCES T X D LOW o NORMAL OPERATION ERROR RESET I RESET ALL ERROR FLAGS PE OE FE REQl EST TO SEND HIGH FORCES RTS Ol TPlT TO ZERO I ITER IAL RESET HIGH RETURNS 8251 TO MODE I STRLCTIO FORMA...

Page 117: ...er PCB sn 8253 2 4576 MHz i P RD CLKO 8251 ITMI O I RX C ITM2 0 r TXC 161 16 TEt TL t t _ CP BIT SYNC CLOCK GEN TM4 L o 2 r RTI Figure 3 21 Communications Controller Circuit for Asynchronous Operation 3 52 STl ...

Page 118: ...0 0 0 0 0 1 o 0 000 0 0 0 300 512 0 0 0 0 0 0 1 0 o 0 000 0 0 0 200 768 0 0 0 0 0 0 1 1 o 0 0 0 0 0 0 0 135 100 1536 0 0 0 0 0 1 1 0 o 0 o 0 0 0 0 0 75 2048 0 0 0 0 1 0 o 0 o 0 000 0 0 0 50 3072 0 0 0 0 1 1 o 0 o 0 000 0 0 0 Count Rate 2457600 RxC or TxC x 16 Hz 3 6 4 2 SYNCHRONOUS OPERATING MODE The mode instruction word for synchronous operation is shown by Figure 3 22 Figures 3 23 and 3 24 show...

Page 119: ...E 1 0 XTERNAI SYNC Dt TE T SYNDEr IS AN INPl r SYNDEr IS AN Ol TPlTT SINGU I SIN CHARACTER SYNC LE CHARACTER au CHARACTER 0 DOl Figure 3 22 Synchronous Mode Instruction Word RT sn 8253 2 4576 MHz p RD TI C lFKO ______ CP 161 16 BIT SYNC CI OCK GEN 8251 T 0 1 00 1 STI f 4 RTI Figure 3 23 Communications Controller Circuit for Synchronous Operation Using External Clock ...

Page 120: ...53 2 4576 MHz p RD c r comrOller rcn 8251 O RXC TXC 161 16 TE CLKO TL f CP BIT SYNC CLOCK GEN TM4 1 O C J STI r RTI Figure 3 24 Communications Controller Circuit for Synchronous Operation Using Internal Clock 3 55 ...

Page 121: ...0 0 0 0 0 0 o 0 1 0 0 0 0 0 0 0 9600 256 0 0 0 0 0 0 o 1 o 0 0 0 000 0 4800 512 0 0 0 0 0 0 1 0 000 0 0 0 1 0 2400 1024 0 0 0 0 0 1 o 0 o 0 0 0 0 000 1200 2048 0 0 0 0 1 0 o 0 o 0 0 0 0 000 600 4096 0 0 0 1 0 0 o 0 o 0 0 0 0 0 0 0 300 8192 0 0 1 0 0 0 o 0 o 0 0 0 0 0 0 0 200 12288 0 0 1 1 0 0 o 0 000 00000 100 18204 0 1 0 0 0 1 1 1 000 1 1 1 o 0 75 24756 0 1 1 0 0 0 o 0 101 1 0 1 o 0 Count Rate 24...

Page 122: ... lists the Baud rate setting codes when operation with business machine timing 2 4576 MHz RTD sn 8253 CLKO o __ _ j RXC TXC ITM2 8251 TE 161 16 p TI 1 1 CP RD L r_ BIT SYNC CLOCK GEN I RT1 Figure 3 25 Communications Controller Circuit for Business Machine Clock Controller rClJ STI 3 57 ...

Page 123: ...0001 000 9600 16 0 0 0 0 0 0 o 0 000 1 0 0 0 0 4800 32 0 0 0 0 0 0 o 0 o 0 1 000 0 0 2400 64 0 0 0 0 0 0 o 0 o 1 0 0 0 0 0 0 1200 128 0 0 0 0 0 0 o 0 100 0 0 0 0 0 600 256 0 0 0 0 0 0 o 1 o 0 0 0 0 0 0 0 300 512 0 0 0 0 0 0 1 0 o 0 0 0 0 0 0 0 200 768 0 0 0 0 0 0 1 1 000 0 0 0 0 0 135 1138 0 0 0 0 0 1 o 0 011 100 1 0 100 1536 0 0 0 0 0 1 1 0 o 0 0 0 0 0 0 0 75 2048 0 0 0 0 1 0 o 0 o 0 0 0 0 0 0 0 ...

Page 124: ...ND INSTRUCTION OVERRUN ERROR OE FLAG IS SET WHEN THE CPU DOES NOT READ A CHARACTER BEFORE THE NEXT ONE BECOMES AVAILABLE IT IS RESET BY ER BIT OF COMMAND INSTRUCTION DOES NOT INHIBIT 8251 OPERATION BUT OVERRUN CHARACTER IS LOST FRAMING ERROR ASYNC ONLY FE FLAG SET WHEN VALID STOP BIT IS NOT DETECTED AT THE END OF EVERY CHARACTER DOES NOT INHIBIT 8251 OPERATION FE IS RESET BY THE ER BIT OF THE COMM...

Page 125: ...tem can generate tones ranging over two octaves in frequency at specified note lengths intensities and tempos A functional block diagram of the sound control system is shown in Figure 3 27 The sound system speaker is mounted near the front ofthe main unit An operator s volume control is also provided f 1PDl771 C 006 DB 0 TO 7 IOWO WR IORO RD CS CS 4 MHz CLK Figure 3 27 Sound Control Block Diagram ...

Page 126: ...26 describes the pin assignments CONTROLLER G9PFCU PCB CN6 CN7 VOLUME Figure 3 28 Location of Sound Interface Connectors Table 3 26 Sound Interface Pin Assignments CONNECTOR PIN SIGNAL CN6 1 Volume In Volume Interface 2 Volume Out 3 Ground 4 Ground CN7 1 SP Speaker Interface 2 SP unlrUller r D 3 61 ...

Page 127: ...d Scale commands SO to S7 Status information if HEX value is 80 all the write commands are accepted if HEX value is 00 only the Beep command is accepted Table 3 28 Sound Control Commands FIRST COMMAND SECOND COMMAND DATA BUS DATA BUS COMMAND 7 65432 1 0 MUSIC EXPRESSION 7 6 5 4 3 2 1 0 Music Notes 0 0 1 1 0 0 0 1 Volume Illegal 0 1 0 0 0 0 0 0 Beep Notes Piano 0 1 0 0 0 0 0 1 20 ms 0 0 1 1 1 OXX M...

Page 128: ... 0 1 1 1 0 0 1 0 Forte 0 1 1 1 0 0 1 1 Table 3 29 Sound Scale Commands FIRST COMMAND NOTE TONE SECOND COMMAND NOTE DURAnON DATA BUS DATA BUS COMMAND 7 6 5 4 3 2 1 0 COMMAND 7 6 543 2 1 0 Illegal 0 0 0 0 0 0 0 0 Moderately emphatic 0 1 0 OXXXX C 0 0 0 0 0 0 0 1 rhythm C 0 0 0 0 0 0 1 0 Emphatic rhythm 0 1 0 IXXXX D 0 0 0 0 0 0 1 1 Note without point 0 1 OXOXXX D 0 0 0 0 0 1 0 0 Note with point 0 1 ...

Page 129: ... 0 1 1 0 0 Illegal 0 1 0 XX 1 I 0 C 0 0 0 0 1 1 0 1 Illegal 0 I o X X I I I C 0 0 0 0 I 1 1 0 D 0 0 0 0 1 1 1 1 D 0 0 0 1 0 0 0 0 E 0 0 0 1 0 0 0 1 F 0 0 0 1 0 0 1 0 F 0 0 0 I 0 0 1 1 G 0 0 0 I 0 1 0 0 G 0 0 0 1 0 I 0 I A 0 0 0 1 0 1 I 0 A 0 0 0 I 0 I I 1 B 0 0 0 1 1 0 0 0 C 0 0 0 I 1 0 0 1 C 0 0 0 1 1 0 1 0 D 0 0 0 I 1 0 I 1 D 0 0 0 1 1 1 0 0 E 0 0 0 1 1 1 0 I 0 0 0 I I 1 I 0 Illegal Through 0 0 ...

Page 130: ... D LO J D D D D TMID rr 11 l 1 D D TM20 TM6 TM5 D 1 TM3 17 ASYNCHRONOUS TMI 3 TM2 1 TM4 2 D LOt D D D D TMID r i1w D D TM20 TM6 TM5 D I TM3 1 roJOI D 17 I I l l I 1 n BUSINESS MACHINE CLOCK TMI 2 TM2 1 TM4 1 DLO D D D D DLO TMID rr i1 D D TM20 TM6 TM5 D I I TM3 i DI nil MONOCHROME D1SPLAY TM3 2 TM5 SHORTED TM6 1 D D D D TMID rr 11 D D TM20 TM6 TM5 D I I TM3 TM4 17 COLOR DISPLAY TM3 1 TM5 OPEN TM6 ...

Page 131: ...nt and overvoltage protection Ripple voltage does not exceed 50 mV at any dc output except the 24 V output where the ripple voltage does not exceed 100 mV Spike noise voltage is less than 250 mVon any output If an overload or overvoltage condition exists on any of the dc outputs the unit automatically shuts down until the condition is corrected and the power is recycled off and on The power supply...

Page 132: ...hown in Figure 4 2 and listed in Table 4 1 AciN FUSE PCOUn 7 RELAY CONTACTS RATED AT 0 5 1A AT 125 Vac NOISE FILTER Figure 4 1 System Power Supply Block Diagram 24 V 5 V 12V 2 V 5 V SG Ac 115 V OUT R L O__ POF IN LESS THAN 1 10 MS POF I I Dc ac OUTPUTS J POF J I OWER ENABLEDJ ON OUTPUT OFF ...

Page 133: ...RT TO FAN SW TO FDD A TO FDD B 5V PIN 3 5V PIN 5 24V PIN 1 SG PINS 2 4 6 FG PIN 7 Figure 4 2 Power Supply Interconnection Diagram 8 1 1 1 1 16 9 TO FROM CARD CAGE BUS SV PINS 2 7 l2V PIN 5 12V PIN 3 5V PIN 4 SG PINS 1 8 POF PIN 6 Power Supply 4 3 ...

Page 134: ...upply Pin Command Assignments CN2 CN2 PIN DESCRIPTION PIN DESCRIPTION NUMBER NUMBER 1 115 Vac 9 115 Vac 2 Ground 10 Ground 3 12 Vdc 11 12 Vdc 4 5 Vdc 12 5 Vdc 5 POF 13 24 Vdc 6 5 Vdc 14 Ground 7 5 Vdc 15 5 Vdc 8 Ground 16 Ground 4 4 ...

Page 135: ...nsigned Arithmetic Operations in Binary or Decimal Multiply and Divide Instructions 24 Operand Addressing Modes Assembly Language Compatible with the IlPD8080 8085 Complete Family of Components for Design Flexibility PIN CONFIGURATION GND Vee AD14 AD15 AD13 A16 S3 AD12 A17 S4 AD11 A18 S5 AD10 A19 S6 AD9 SHE S7 AD8 MN MJ AD7 AD AD6 HOLD RO GTO AD5 HLDA Ro GT1 AD4 WR COCi AD3 M iO Si AD2 DTIR Si AD1...

Page 136: ...N Data Enable This is the output enable for the IIPD8282 8287 transceivers It is active low during each memory and I O access and INTA cycles 27 DT R Data Transmit Receive Used to control the direction of data flow through the an i 28 MilO Memory IO Status This is used to separate memory access from I O access 29 WR Write Oepending on the state of the MilO line the processor is either writing to I...

Page 137: ...ER FilE DATA POINTER AND INDEX REGS SWORDS 16 BIT AlU FLAGS BUS INTERFACE UNIT I RELOCATION REGISTER FilE SEGMENT REGISTERS AND INSTRUCTION POINTER 5 WORDS BUS INTERFACE UNIT 6 BYTE INSTRUCTION aUEUE CONTROL TIMING ClK RESET READY MN MX GND Vee DT R DEN ALE aSa as Al 3 ...

Page 138: ...or extended periods may affect device reliability Ta O C to 70 C VCC 5V 10 LIMITS TEST PARAMETER SYMBOL MIN MAX UNITS CONDITIONS Input Low Voltage VIL 0 5 O B V Input High Voltage VIH 2 0 VCC 0 5 V Output Low Voltage VOL 0 45 V 10l 2 5 mA Output High Voltage VOH 2 4 V 10H 400pA Power Supply Current ICC pPDBOB6 340 mA Ta 25 C pPDBOB6 2 350 mA Input leakage Current III 10 pA OV VIN VCG Output leakag...

Page 139: ... Delay TCLLH 80 ALE Inactive Delay TCHLL 85 Address Hold Time to ALE Inactive TLLAX TCHCL 10 TCHCL l0 Data Valid Delay TCLDV 10 110 10 Dat8 Hold TIme TCHDX 10 10 Data Hold Time After WR TWHDX TCLCH 30 TCLCH JO Con trol Active Delay 1 TCvCTV 10 110 10 Control Active Delay 2 TCHCTv 10 110 10 Control Active Otlay TCvCTX 10 110 10 Address Flolt 10 READ Active TAlRL 0 0 RD Active Delay TCLRL 10 165 10 ...

Page 140: ...eLK 8284 QUlpun MIlO ALE ROY 8284 Inpun Q READY 8086 Inputl AEAC CYCLE D lWR INTA VOH OllA AI 6 TIMING WAVEFORMS Minimum Complexity Systems r I ...

Page 141: ...gnal witch between VOH ana VOL unle otherwise specified ROY is sampled ne r the and of T2 T3 TW to determine if TW machines tata are to be insarted Two INTA cycl run back to back TheI POB086 local AODR Data Bus Is floating during both INTA cyclas Control signals shown for second INTA cycle Signal at POB284 are shown for refarence only All timing maasurements ara made at 1 5V unle otherwise noted A...

Page 142: ...AZ TCLAX 80 TCLAX 50 SIItU5 Valid to ALE Htgh TSVLH 15 15 See Note 1 5t u Vllid to MCE High T5VMCH 15 15 See Notl I CLK Low to ALE Vllid TCLLH 15 15 See Note 1 CLK Low to MCE High TClMCH 15 15 See Note 1 ALE Ineet vl Dalay See Note 1 TCHLL 15 15 MCE InactIve Delay See Note 1 TCLMCl 15 15 Dltll Vllid Delay TCLDV 10 110 10 60 Dltl Hold TIme TCHDX 10 10 Control Active DeilY See Note 1 TCVNV 45 45 Con...

Page 143: ...imum Mode System Usi J LPB8288 Controller Q elK veL aScl as J ro EXCEPT t IAL TI BHE S7 A19 S6AUyS3 ALE 8288 OUTPUT t ROY 8284 INPUT I READ CYCLE ill A15 ADO OT A 8288 OUTPUTS MRoe DR lORe DEN ____________________J T3 AI 9 ...

Page 144: ...mum Mode System Using IlPB8288 ontroller Con t V T _ _ _ J ____ _ NOTES D A 1I h_tdtbetwMnVOHMdVOL O if ROY iI thtendofT2 T3 Twto ifTW mechinM to be iMllrted 1c add ilWllid firwl NTA Two NTA eye run beck to blJck The _ ADOAto I II ftoetingdurineboth NTA cvcteL Cofth Ol for poiftW it thown tor ond INTA cytM SiIMh 182M or 8281 1hown for l l f I II IDd_ iiiiiii MWTC AMWC IOAC IOWC Alowe INTA gEN the ...

Page 145: ... SEQUENCE TIMING elK NMI INTR SIGNAL ____ i EsT NOTE CD Setup requirements for asynchronous signals only to guarantee recognition at next elK NOTE CD The coprocessor may not drive the buses outside the region shown without risking contention for Maximum Mode only AI II ...

Page 146: ...erdip ITEM MILLIMETERS INCHES A 51 5 MAX 2 03 MAX B 1 62 MAX 0 06 MAX C 2 54 0 1 0 1 0 004 D 0 5 0 1 0 02 0 004 E 48 26 0 1 1 9 0 004 F 1 02 MIN 0 04 MIN G 3 2MIN 0 13 MIN H 1 0MIN 0 04 MIN I 3 5 MAX 0 14 MAX J 4 5 MAX 0 18 MAX K 15 24 TYP 0 6 TYP L 14 93 TYP 0 59 TYP M 0 25 0 05 0 01 0 0019 HOLD HOLD ACKNOWLEDGE TIMING PACKAGE OUTLINE IlPD80860 ...

Page 147: ...ts False Start Bit Detector Automatic Break Detect and Handling pPD8251A Synchronous Five 8 Bit Characters Internal or External Character Synchronization Automatic Sync Insertion Single or Double Sync Characters Baud Rate 1X Mode DC to 56K Baud J 1PD8251 DC to 64K Baud J 1PD8251A Full Duplex Double Buffered Transmitter and Receiver Parity Overrun and Framing Flags Fully Compatible with 8080A 8085 ...

Page 148: ...ally in asynchronous operations which relieves the processor of this task 3 The Receiver is prevented from starting when In break state by a reftned Rx initialization This also prevents a disconnected USART from causing unwanted Interrupts 4 When a transmission IS concluded the TxD line will always return to the marking state unless SBRK IS programmed 5 The Tx Dlsahle command IS prevented from hal...

Page 149: ...ut Voltages Supply Voltages Ta 25 C TRANSMIT hO T RDY hE he SVNDET uPD8251l SYNDET BD PD8251A 0 C to 70 C _65 C to 150 C 0 5 to 7 Volts 0 5 to 7 Volts 0 5 to 7 Volts COMMENT Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in th...

Page 150: ... Ou tpu 1 Low Vol tage Val 0 45 0 45 V PDB251 A IOL 2 2 mA PDB251 IOH 10C A Output High Voltage VOH 2 4 2 4 V POB251A IOH 40G A 50 10 VOUT 0 45V Data Bus Leakage IDl A 10 10 VOUT VCC Input Load Current III 10 10 A At 5 SV Power Supply Current ICC 45 BO 100 PDB251A All OutputS mA Logic 1 LIMITS TEST CAPACITANCE PARAMETER SYMBOL MIN TY MAX UNIT CONDITIONS Input Capacitance elN 10 pF tc 1 MHz 1110 Ca...

Page 151: ...aud Ral cY RecE E InOul Clock l e Juenc 0 j BiJud Rate DC 56 64 16 Baud Rolle DC 0 310 64 Baud Ratt rae 0 6 Reee er l Out C O F u le W dT IRPW 1X BiJud Ralt c 16x and 64x Baud Rate cy Reel l I put CtOl Pulle De a IRPD 1 Baud Rate CY 16 d 64 Baud Rail 3 CY T ADY Dela r m Centl 0 D ad T 16 PD8 T C L SO pf R RDY Dt la 0 CI 1 01 DatJ a 1 R 0 24 CY 1 I nal SY NDE T Delay Irom CI lt S 25 24 e 01 Da a B ...

Page 152: ...NT SAMPLING pULSE TRANSMITTER CLOCK AND DATA IR BAUD COUNTER sr4RTS HERE START BIT DATA81T DATA 81T IRPW _ _ _ _ _ j J RECEIVER CLOCK AND DATA Til ROY _ _ _ J 1 DON T CARE OATAIN10Bj C O WRITE DATA CYCLE PROCESSOR USART RII RDY DATA OUT 10 8 _ __ O A TA F L O A T__ f ClI5 READ DATA CYCLE PROCESSOR USART TIMING WAVEFORMS ...

Page 153: ...CR 1f tRR X _ I tRD L tOF OATAOUT ___________________ tJl ID B I 1 AR I IRA r CD tl 1IAR f I RAy READ CONTROL OR INPUT PORT CYCLE PROCESSOR USART Tx EMPTY _ h READY STATUS BIT r READY PIN c 5 W S8RK T OATA oa OO LDOl OJ DlIIDO UlXI L o _NM rHO DATA CHAR 1 DATA CHAR DATA CHAR 3 EXAMPLE FORMAT 7 BIT CHARACTER WITH PARITY AND STOP 81TS TRANSMITTER CONTROL AND FLAG TIMING ASVNC MODE DATA CHAR 4 A2 7 ...

Page 154: ... BITS rn RECEIVER CONTROL AND FLAG TIMING ASYNC MODE h EMPTY I 1 Ix R A D Y t STATU BIT I T READY EXAMPLE FORMAT BIT CHARACTER WITH PARITY AND 2 SYNC CHARACTERS TRANSMITTER CONTROL AND FLAG TIMING SYNC MODE lll T S 8 f ljL JV R f 1 l RR R 8 1 1 C D J t d 0 h TIMING WAVEFORMS CaNT XIT HUNT MOOf SETSYNDET STATUSBITI SE T SYNOf T ST A TUS 81T I RECEIVER CONTROL AND FLAG TIMING SYNC MODE Notes 1 Inter...

Page 155: ...us marie anci 4 5 limps for the nsvnchronouS mocie I 10 WR Wrlle Oat 1 A ero on thiS Input nq ucts hl USART 1 TO accept the data Or control word wh Ch the processor IS wrl lnq out on thp data bus 13 RD Read Data A zero on thiS Input nsTruC S the USART to place the data Or status nformation I onlO the Data Bu tor the prOCeSSOr 10 read I I 12 C D ContrOI Dola o 0 0 J I WR and RD Inputs nfo ms the US...

Page 156: ...r In half duplex TxE can be used to signal end of a transmission and request the processor to turn the Ime around The TxEn bit in the command instruction does nOt effect TxE In the Synchronous mode a one on this out put Indicates that a Sync character or charac ters are about to be automatically transmitted as fillers because the next data character has not been loaded 9 TxC Transmitter Clock The ...

Page 157: ...r I l In l lttle ThF In t rll 1 tI ell lt Il 1 Sync mode rnci SYNDET Then lunctlons IS In Outpul or npul reSpecllvely In Ihe rnl rn 1 Sync nlo l lh SYNDE T oulpul rll go 10 d on hl ll Iht PD8251 h l luCrler Iht SYNC Ch tI H IPI rll tilt Rt cerIH mode II jouillp SYNC ChtirilC Ibl sync Oper lllon h IS 111 1 D U gl lmmed SYN E T l1 go 10 ant In ttl mldd e at the IdSt brt of the second SYNC ChiJlClCle...

Page 158: ...r software reset after the device operation has once been established The 1PD8251 and J 1PD8251A cannot transmit until the TxEN Transmitter Enable bit has been set by a Command Instruction and until the CTS Clear to Send input is a zero TxD is held in the marking state after Reset awaiting new control words OPERATIONAL DESCRIPTION The USART must be loaded with a group of two to four control words ...

Page 159: ...ynchronous or Synchronous communication modes Understanding how the Mode Instruction controls the functional oiJerat on of the USART IS easiest when the deVice is conSidered to be two separate components one asynchronous and the other synchronous which share the same support circuits and package Although the format defll1ltlon can be changed at will or on the fly the tw J modes will be explained s...

Page 160: ...er a valid STOP bit the input character is loaded into the parallel Data Bus Buffer of the JPD8251 and JPD8251 A and the RxRDY signal is raised to indicate to the processor that a character is ready to be fetched If the processor has failed to fetch the previbus character the new charac ter replaces the old and the overrun flag OEI is set All the error flags can be reset by setting a bit in the Co...

Page 161: ...uffer becomes empty the SYNC character s loaded directly following the Mode Instruction will be automatically inserted in the TxD data stream The SYNC character s are inserted to fill the line and maintain synchronization until new data characters are available for transmission If the f PD8251 and f PD8251A become empty and must send the SYNC character s the TxEMPTY output IS raised to signal the ...

Page 162: ...I I I 1 H l l 1 HIE T H I I i I I I I b T I BITS I ITS 81T BITS __ PARITY E AAlE I EII jABlE I 0 ll SABl f 1 L __________ EIIE NPARITY GEII jERATIO l CHECK EVEI j o ODD L _ _ _ _ _ _ _ _ _ _ _ EXTERNAL SYNC DETECT 1 SYNDET IS AN INPUT o SYNDEr IS AN OUTPUT L _ _ _ _ _ _ _ _ _ _ _ _ _ INGLE CHARACTER SYNC SYNC CHAR 1 1 SINGl E SYNC CHARACTER o DOUBt E SYNC CHARACTER PROCESSOR BYTES I O BITS CHARI f...

Page 163: ...other conditions which require a response from the processor The IlPD8251 and IlPD8251 A have features which allow the processor to read the device status at any time A data fetch is issued by the processor while holding the C O input high to obtain device Status Information Many of the bits in the status register are copies of external pins This dual status arrangement allows the IlPD8251 and IlP...

Page 164: ...1 S est t bv the fA b 01 the Command InSTruct on PE does nOI t I b ope_ t on 01 the J lPD8151 and JjPD8151A OVERRUN ERROR The DE Ilag os sel when e CPU does nOI f ad a character btfOfe the nelll one come avaIlable 1 re 1 bv the fR b 01 the Command nll uel on OE dMS not ntub t OPe at on 01 tne P08251 and P08251 A but tne p e llIOUIly ov rrun cha aet II loll FRAMING ERROR lAsvnc onlyl Tne FE lIa9 Nt...

Page 165: ...OC to 9600 BAUD PHONE llNF INTER fACE TEl EPHONE LINE ASYNCHRONOUS INTERFACE TO TELEPHONE LINES SYNCHRONOUS TERMINAL OR PERIPHERAL DEvICE SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL OEVICE SYNC MODEM PHONE LINE INTEA FACE TELEPHONE LINE SYNCHRONOUS INTERFACE TO TELEPHONE LINES A2 19 ...

Page 166: ...572MAX K 15 24 L _ 0225 MAX 06 1 I K L 1 J C M 00_100 I Ceramic ITEM MILLIMETERS INCHES A 362 MAX 1 43 MAX B 1 59 MAX 0 06 MAX C 2 54 0 1 0 1 0004 0 0 46 0 01 0 02 0 004 E 33 02 0 1 1 3 0 004 F 1 02 MIN 0 04 MIN G 3 2 MIN 0 13 MIN H 1 0MIN 0 04 MIN I 3 5 MAX 0 14 MAX J 4 5 MAX 0 18 MAX K 15 24 TYP 0 6 TYP L 14 93 TYP 0 59 TYP M 0 25 0 05 0 01 0 002 PACKAGE OUTLINES J IPD8251C J LPD8251AC lPD8251D ...

Page 167: ...e Data Scan Equal Format a Track Write Deleted Data Seek Recalibrate Restore to Track 0 Sense Interrupt Status Sense Drive Status Address mark detection circuitry is internal to the FDC which simplifies the phase locked loop and read electronics The track stepping rate head load time and head unload time may be programmed by the user The JPD765 offers many additional features such as multiple ecto...

Page 168: ...Tvpical values for Ta II 2SoC and nominal supply Yoltage READY WAITE PROTECTfTWQ SIDE INDEX FAULT TRACK 0 UNIT SELECT 0 UNlTSELECT 1 MFM MODE RWISEEK HEAD LOAD HEADSELECT LOW CURRENT DIRECTION FAULT RESET STEP _10 C to 70oe 55 eto 150oe 0 5 to 7 Volts 0 5 to 7 Volts 0 5 to 7 Volts 1 Watt TEST UNIT CONDITIONS V V V IOl 2 0 mA V IOH 200 A V V mA A VIN VCC A VIN OV A VOUT VCe A VOUT 0 45V BLOCK DIAGR...

Page 169: ...RetUrn 2 WCK Write Clock Input WrItt deal me to FDO FM tiOO kHz MFM 1 MHz with pul wkith of 210 N tor both FM net MFM 22 RDW Reid o u Window Input Ph Lock LO Op Ganamad by PLL and ul8d to pl det8 from FDO 23 ROD A_e g I FOO Reed cIMa from FDD conulnlng clock ancI blu 20 veo VCOSync 0u1PU Ph_ Lock Loop Inhibits veo in PLL when 0 Howl enables VCO when 1 25 WE Write En t lt 0u1PU FOO Enlbl_ wtlttl de...

Page 170: ... TCp 20 00 ns WoA Delay Time from WCK f TCO 20 00 n ROO Active Time High TROO 40 n Window Cycle Time TWCY 2 0 0 MFM a MFM Window Hold Time to from ROO TROW TWRD 15 n USO 1 Hold Time to Ifi Ii SEEK t TUS 2 SEEK RW Hold Time to LOW CURRENT TSD 7 DIRECTIDN 1 LOW CURRENT DIRECTION Hold Tim to TDST 1 0 FAULT RESET STEP t USO Hold Time from FAULT TSTU 5 0 8 MHz Clock RES ET STEP t Period STep Acti Time ...

Page 171: ...4SV for a logic 0 Timing measure ments are made at 2 QV for a logic 1 and a BV for a logic 0 Clocks are driven at 3 QV for a logic 1 and O 3V for a logic 0 Timing measure ments are made at 2 4V for a logic 1 and O 65V for a logic 0 TIMING WAVEFORMS pF All Pins Except pF Pin Under Test Tied to AC pF Ground PROCESSOR READ OPERATION PROCESSOR WRITE OPERATION AO Cs DAcK x X ____ TAR I J TRA RD TRR_t L...

Page 172: ...ION STABLE lV _ Jt ltu 1 i tsu r X f I__ j ItOSI tSOt I r DIRECTION _____ X tDST i t TU 1 STEP _ _ _ _ _nS_T_D_ _ _ II tSTP j I 1 1 tsc 4 1 USO RWISEEK FDD READ OPERATION READ DATA I i TRDD iTWRD j TRDW l _ _ _ I READ DATA WINDOW X ll 1 1 1 _ TWCy Note Either polarity data windOW is valid A3 6 TERMINAL COUNT TC n I TTC RESET H RESET l t I TRST FLT RESET 1 FAULTRESET FILE UNSAFE RESET I TFR INDEX 1...

Page 173: ... is set FOC will not accept read or write command DB FOC Busy CB A read or write command is in process FOC will not accept any other command oBS Execution Mode EXM This bit is set only during execution phase in non OMA mode When DBS goes low execution phase has ended and result phase was started It operates only during NON OMA mode of operation DB6 Data Input Output DID Indicates direction of data...

Page 174: ...US D 03 2 0 Do RECALIBRATE X C US usa W SENSE INTERRUPT STATUS W W EOT Command W W GPl Result STO W STP PCN Execution Data compared between the SPECIFY FDD and main system Command W Result ST 0 Status information after W SRT HUT ST Command execution W HlT NO ST SENSE DRIVE STATUS C Sector 10 information after Command W Command execution W X X X HO US usa SCAN HIGH OR eaUAl Result ST3 Command W MT ...

Page 175: ...ull Re ull ExecutIon READ A TRACK o MF o 0 0 HO US1 W_ O W GeL on W W 5 AEAOIO 0 X HO US USO 2 C FORMAT A TRACt W W ____ 0 S 2 SCAN EOUAL tiO US Ar W _ N W OT Gee 5 T REMARKS Secto LD nformal onproor 10 Command a eCUI on 08 a a de 0eIwel n he FDD and rna ntern FDC rl 11 datlf ld f om on hole w EDT Stalus nlormaIIOrl ltfr CommandeKecul on Sl lOr IOu lormaTranalte CommandeKeculion The 1 1 correcllD ...

Page 176: ...umber on a Cylinder During Read or Write operation FOe will stop date transfer after a sector equal to EOT GPL stands for the length of Gap 3 During Read Write commands this value determines the number of bytes that veos will stay low after two eRe bytes During Format command it determines the size of Gap 3 H stands for head number 0 or 1 as specified in 10 field H0 stands for a selected head numb...

Page 177: ...f STP 2 then alternate sectors are read and compared US stands for a selected drive number aor 1 PROCESSOR INTER FACE During Command or Result Phases the Main Status Register described earlier must be read by the processor before each byte of information is written into or read from the Data Register After each byte of data read or written to Data Register CPU should wait tor 12 Is before reading ...

Page 178: ...e Result Phase the command is automatically ended and the pPD765 is ready for a new command After the Specify command has been sent to the pPD765 the Unit Select line USO and US1 will automatically go into a polling mode In between commands and between step pulses in the SEEK command the lPD765 polls all four FDD s looking for a change in the Ready line from any of the dri es If the Rea dy line ch...

Page 179: ...ds_ This time out is particularly valuable when a diskene is copied from one drive to another_ If the FOC detects the Index Hole twice without finding the right sector indicated in R l then the FOe sets the NO No Data flag in Status Register 1 to a 1 high and terminates the Read Data Command Status Register 0 also has bits 7 and 6 set to aand 1 respectively j After reading the 10 and Data Fields i...

Page 180: ... Command operates in much the same manner as the Read Command The following items are the same and one should refer to the Read Data Command for details Transfer Capacity Head Unload Time Interval EN End of Cylinder Flag 10 Information when the processor terminates command see Table 2 NO No Data Flag Definition of OTL when N 0 and when N F 0 In the Write Data mode data transfers between the proces...

Page 181: ...ette to be formatted with non sequential sector numbers if desired The processor must send new values for C H R and N to the uP0765 for each sector on the track If FOC IS set for OMA mode it Will issue 4 DMA requests per sector If It IS set for mterrupt mode It will Issue tour interrupts per sector and the processor must supply C H Rand N load for each sector The r ontents of the R register IS Inc...

Page 182: ...DD DProcessor Scan Hi or Equal a a DFDD DProcessor 1 a DFDD Dprocessor Table 4 If the FOC encounters a Deleted Data Addres Mark on one of the sectors and SK 0 then it regaros the sector as the last sector on the cylinder sets CM Control Mark flag of Status Register 2 to a 1 hig and terminates the command If SK 1 the FOC skips the sector with the Deleted Address Mark and reads the next sector In th...

Page 183: ... SEEK END flag in Status Register 0 is set to 1 high and the command is terminated If the Track 0 signal is still low after 77 Step Pulse have been issued the F DC sets the SE SEE K END and EC EQUIPMENT CHECK Ilags 01 Status Register 0 to both 1s highs and term inates the command after bits 7 and 6 of Status Register 0 is set to 0 and 1 respectively The ability to do overlap RECALIBRATE Commands t...

Page 184: ...OMA or NON OMA operation is made by the NO NON OMA bit When this bit is high NO the NON OMA mode is selected and when NO 0 the OMA mode is selected SENSE DRIVE STATUS This command may be used by the processor whenever it wishes to obtain the status of the FOOs Status Register 3 contains the Drive Status information stored internally in FOe registers INVALID If an invalid command is sent to the FOe...

Page 185: ... FDD is in the not ready state and a read or write command is issued th is flag is set If a read or write command is issued to Side 1 of a single sided drive then th is flag is set HD This flag is used to indicate the state of the head at Interrupt US 1 These flags are used to indicate a Drive Unit uso Number at Interrupt_ STATUS REGISTER 1 EN When the FDC tries to access a Sector beyond the final...

Page 186: ...it condition of eQual is satisfied this flag is set Scan Not SN During executing the SCAN Command if the Satisfied FOe cannot find a Sector on the cylinder which meets the condition then this flag is set Bad BC This bit is related with the NO bit and when the Cylinder content of C on the medium is different from that stored in the lOR and the content of C IS FF then this flag is iiet Missing MD Wh...

Page 187: ... H I J K L M Ceramic MILLIMETERS 51 5 MAX 1 62 MAX 2 54 0 1 0 5 0 1 4B 26 0 1 02 MIN 3 2 MIN 1 0 MIN 3 5 MAX 4 5 MAX 15 24 TYP 14 93 TYP 0 25 0 05 Plutic MILLIMETERS 51 5 MAX 1 62 2 54 0 1 0 5 0 1 4B 26 1 2MIN 2 54 MIN 0 5MIN 5 22 MAX 5 72 MAX 15 24 13 2 0 1 0 25 0 05 INCHES 2 03 MAX 0 06 MAX 0 1 0 004 0 02 0 004 1 9 0 004 0 04 MIN 0 13MIN 0 04 MIN 0 14 MAX 0 1B MAX 0 6 TYP 0 59 TYP 0 01 0 0019 IN...

Page 188: ...table video raster parameters o Technology Single 5 volt NMOS 40 pin DIP o DMA Capability Bytes or word transfers 4 ciock periods per byte transferred System Considerations The GDC is designed to work with a general purpose microprocessor to implement a high performance com puter graphics system Through the division of labor established by the GDC s design each of the system components is used to ...

Page 189: ...The display memory controller s tasks are numerous Its primary purpose is to multiplex the address and data infor mation in and out of the display memory It also contains the 16 bit logic unit used to modify the display memory con tents during RMW cycles the character mode line counter and the refresh cou nter for dynamic RAMs The memory controller apportions the video field time between the var i...

Page 190: ...nd of any previous operation The number of parameter bytes supplied with a command is cut short by the receipt of the next command byte A read operation from the GOC to the microprocessor can be terminated at any time by the next command The FIFO changes direction under the control of the sys tem microprocessor Commands written into the GOC always put the FIFO into write mode if it wasn t in it al...

Page 191: ...rclockwise Drawing Directions Figure drawing requires the proper manipulation of the address and the pixel bit position according to the drawing direction to determine the next pixel 01 the figure To move to the word above or below the current one it is necessary to subtract or add the number of words per line in display memory This parameter is called the pitch To move to the word to either side ...

Page 192: ... bytes by the appropriate PRAM command the GCHRD command can be used to draw the bytes into display memory starting at the cursor The zoom magnification factor for writing set by the zoom command controls the size of the character written into the display memory in integer multiples of 1 through 16 The bit values in the PRAM are repeated horizontally and vertically the number of times specified by...

Page 193: ...dra JI nd nVlh r t OIspiay Partition 4 starting itddress and Graphics and Mixed Graphics and Character Modes SA02 l SAD2 LEN2l I 0 o ISA02 H WD IIM I LEN2 t 0i yPartition 2 startIng IdcIreu Ind Ief1gthwithllnllgeldentlty DilaSln rea 1 cL I PTN RA l0 11 12 13 14 15 GCHR8 GCHR7 GCHR6 GCHRS GCHR4 GCHR3 GCHR2 GCHA 1 figure drawing to pattern P dotted hed etc lines Iii Poltemol u_l L r I t memory with ...

Page 194: ...s Horizontal Front Porch Constraints 1 If the display ZOOM function is used at other than lX HFP 2 Display Word Cycles 4 clock cycles 2 If the GDC is used in the video sync Slave mode HFP 4 Display Word Cycles 8 clock cycles 3 If the Light Pen is used HFP 6 Display Word Cycles 12 clock cycles Horizontal SYNC Constraints 1 If Interlaced display mode is used HS 3 Display Word Cycles 6 clock cycles M...

Page 195: ...he start of the HSYNC interval Once the GOCs are initialized and set up as Master and Slaves they must be given time to synchronize It is a good idea to watch the VSYNC status bit of the Master GOC and wait until after one or more VSYNC pulses have been generated before the display process is started The START command will begin the active display of data and will end the video synchronization pro...

Page 196: ...ly the LSB of the WDAT parameter bytes is used as the pattern in the RMW operations Therefore it is possible to have only an all ones or all zeros pattern In coded character ap plications all the bits of the WDAT parameters are used to establish the drawing pattern The WDAT command operates differently from the other commands which initiate RMW cycle activity It requires parameters to set up the P...

Page 197: ... by the EAD and dAD values Date Reed Commends Read Data from Display Memory RDAT LI_ _L_TY p 1I_o_LI_MO D __ OI ITr nl rType 0 Word lowlhlnhlghbytl low Bytl 01 hl Word only HIghBytIO th Wordonly Using the DIR and DC parameters of the FIGS command to establish direction and transfer count multiple RMW cycles can be executed without speCification of the cursor address after the initial load DC numbe...

Page 198: ...ck Input High Voltaga VCH 3 VCC 1 0 V VCC Supply Current ee 270 Capacitance I 2S C VCC GND OV JJmiJL Param r Symbol Unit Telt Conditlona Input c pacttanc C N 0 pF 110 ClPaenanca eVO 20 pF fc_1MHz V Output CllPlcltance COUT 20 pF unmnsured OV Clock Input CIIpacltance C 20 pF AC Characteristics I O C 10 70 C vcc S OV 10 GND OV Read Cycle GDC CPU limits T Symbol Parameter n Unit Conditions AR Address...

Page 199: ...ler MI U O Condttlonl IpS Input Signe Setup to 20 2XCCLKf IpW Input Signe Width elK Clock l lmlt T Symbol Perimeter MI Ill U O CondlUonl C Clock RI Tim 10 CF Clock Fell Time 10 CH Ctoek High Pul Width Cl Clock Low PUIH Width elK Clock Cycle 200 2000 Timing W veforms Display Memory RMW Timing 2xWCLK 0BiN 16 7 ALE Microprocessor Inlertace Writ Timing I V 1 X V J l J_ r r WCY i A4 12 ...

Page 200: ...rface Read Timing AD Inv lid 4 JAA ___ n_ _ _d__ J ________ AD D80 7 H h 7 m 1K I ACV Mlcroproce or Inlerface DMA Wrlle Timing 2xWCLK AEa DAEa 0 I E W W M roproce or Inlerface DMA Read Timing 2 WCLK DREQ t RE i OK t Q R f DACK 080 7 H _ A4 13 ...

Page 201: ...Aoo 1 11 A17 ALE EF i______xr___t_v LCO 3 t es CSR IMAGE AT BLINK fIe light Pen and External Sync Input Timing 2 WCLK PS LPEN EX SYNC _ _ __ tpW Clock Timing 2I1WCLK r VCH 3 Vel 0 5 Test Level for AC Tesls MISCELLAHEOUS 2 0_ T Polnt 2 0 VIH 2 0 x x VOH 2 0 0 VOL 0 8 YIL 0 ...

Page 202: ...Ul J1Jl____ n Il J ____ JlJL___IL 2xWCLK H BLANK Jr c 1 r 0 ______ J H SYNC ADO 15 LCO 4 X ADO 15 r 1 H t __________________ J p x _ _xpx xra _ _ _ _ _ _ _ ____ JJ Xr J J LCO 4 t r I _ ROW C I I ________________________ J ROW t f J c Jo _ JX _______ V BLANK L _______ V SYNC L I 1 4 1V FRAME I ...

Page 203: ... t _ iY ff l i i 1 L i ODD FlELD i EVEN FIELD ______ __________r_ Video Sync Generalor Paramelers A4 16 1 1H HBLANK r 1 ________________________________jr HSYNC j______ I I VBLANK VSYNC I I I j HFP t HBP t C R 1 I I lHSi 1 lV 1 J L I I fI I n I I I I I 1 I YFP 1 1 I f VBp oo t 1 L F 1 1 YBP 1 iVS ...

Page 204: ...t t A00 15 16 17 tpC t C q t HSYNe t J i t VlEXT X __________ ________x x Display and AMW Cycles 2x Zoom 2xWCLK I ZooIMCl Display Zoomed Dlaplay I RMW IDlapI y or RMW I D ID f D TD4 D D 03 D4 t E iE2f E3iE4iE CIO A1 17 ALE rll II 1 _ I __ l__ 1 O P J 15 J lxO p x u x I I BLANK A4 17 ...

Page 205: ...put Address Input Oal Output Oat Di pI FlMW Output Addr AD 15 C r J HORIZONTAL E HORtZONTAL BACK PORCH BLANKING HSYNC OUTPUT BLANK OUTPUT VI Field nmlng r t RTIC A L N C L k M t VERTlCAL BACK POACH BLANKED UNE5 ACTIVE DISPLAY UNES HORIZONTAL FRONT POACH BlANKING VERTICAL FRONT PORCH BLANKED LINES I z ...

Page 206: ... INTERVAL ADDITIONAL DRAWING INTERVAL WHEN IN FLASH MODE DYNAMIC RAM REFRESH IF ENABLED OTHERWISE ADDITIONAL DRAWING INTERVAL DMA Reque t Interval OMA REOUEST INTERVAL ADDITIONAL DMA REoueST INTERVALS WHEN IN fLASH MODE A4 19 ...

Page 207: ... ot Operation 39 A17 OUT Utilization V rl with Mode of Operation 4 Vee 5V t 10 Character Mode Pin Utilization PIn No N DltlHtlon Function 35 37 A013 to 15 OUT line Counter Bit 0 to 2 Output 3 Al OUT Line_Counter Bit 3 Output 30 A17 OUT Cur or Output Mixed Mode Pin Utilization pt No Functton 35 37 AD13 to 15 INJOUT Addr and Data Btt 13 to 15 38 A16 OUT Attribut Blink nd cte r Lin Count r Output 39 ...

Page 208: ... MIN 0 13 MIN 1 0 MIN 0 04 MIN 3 5 MAX 0 14 MAX 4 5 MAX 0 18 MAX 15 24TYP 06 TYP 14 93 TYP 0 59 TYP 0 25 0 05 0 01 0 0019 I IPD7220C 1 A __________ K _ r _ M 0 15 Plastic ITEM MILLIMETERS INCHES A 515 MAX 2 028MAX B 1 62 0064 C 254 0 1 0 10 0 004 0 05 01 0019 0004 E 48 26 1 9 F 1 MIN 0 047 MIN G 254 MIN 0 10 MIN H 05 MIN 0 019 MIN r 5 22 MAX 0 206 MAX J 572 MAX 0 225 MAX K 15 24 0 600 L 13 2 0 520...

Page 209: ...Appendix B Logic and Schematic Diagrams The APe logic and schematic diagrams are arranged in drawing number sequence B 1 ...

Page 210: ... I I 1 2 V I CNI r p N F r 1i7 Z3 2 5 r 0 6 J R _ _ RI7 R16 J I II L R43 cro PiH V 2 I T CI8 019 I 8 1 t t ti ID4 SG 5 r I I Z6 I 161 IL I R18 R19 I I I t 1 R 2 3 I I 4 2 A V R2D A A 5 POF R40 H I I ll R22 I v 1 Ii 7 vv L ACOUT R21 r f l 9 J r L J t t I I L 2 rl _VV lr R39 l I I I I R44 RVI I I I I R42 C26 H I I 9 15 I k1 R31 R32 l R25 R28 R3D 4_ 5 Z5 07 IZ r r l R24 C21 IT J L 3 C28 t L __ 1 __ 1...

Page 211: ...30 13 C 5G R2 X29 14 12 0 18 24 P23 P27 38 05TB 27 R3 X28 13 11 G1 19 P26 37 PBSTB 27 R4 X27 1 10 G2 5G P25 36 5W5TB 27 X26 9 X1 TO 5G X25 9 8 X2 T1 39 Z3 X24 8 7 X23 6 L5244 OB7 19 17 1A1 1Y1 508 6 086 18 15 1A2 1Y2 5 507 X22 5 OB5 17 13 1A3 1Y3 506 OB4 16 11 1A4 1Y4 9 505 X21 4 OB3 15 8 2A1 2Y1 12 504 4 082 14 6 2A2 2Y2 14 503 X20 CN1 5 5G OB1 13 4 2A3 2Y3 16 502 3 5V OBO 12 2 2A4 2Y4 18 501 X19...

Page 212: ...I 8 IRQ01 8 IRQE1 APU INTA 7 AD INT E 2 IDWOO w 2C 2 IDROO 3 CASO 1 1 1 CITSO r f i CAS1 XOOO w A52 15 VCC 5V GND B 4 I 8288 BUS c so IOWl 3 AMWc 52 9 MADC 2 AE371 I15RE INTA 30 DT R 1 ALE xooo w MCE Pi i EN DEN 16 VCC 5V GND 3 lS373 S n 1 3M 19 l G P L 3 lS373 S 9 3l 19 G L f 3 lS373 9 3H 19 L f1G L l L 5V 3 3K A0081 2 3 5 A0091 2 3 5 A0101 2 3 5 A0111 2 3 5 A0121 2 3 5 A0131 2 3 5 A0141 2 3 5 A0...

Page 213: ...R FO I 4b 31 LS74 Ir r t D1 s 4P 1 4P 0 1 I1R Fa I L A2 A3 A4 15 1H A5 il XDOOl CO A6 AJJ R10 5V El A7 1 AIWCO R9 10K 1 t 1 IORCO 10K 1 R11 1 MWTCO 10K T R7 1 MROCO 10K OWOO 1 7 9 11 OROO 1 4 7 911 WROO 7 3 ROOO 4 5 7 11 5TB01 1 AE371 1 7 11 l AE370 4 11 K0 fli3l LS24O OACK1 4 4 OACK2 L15 RZ 5V 8 DACK3 10K l TC m 1 6 1E as RFSH 4 RF5H1 1Z 7 B7 t c AE373 11 4 7 EO lRST El AO 10 40 3 AOO03 ls67iJ 3 ...

Page 214: ...tttttttHrr__t_t_rt_ I 1 28____ 4_ r_ _ g _ i 32 rz7 3 2A 6 2 02 11 5 A3 D3 13 4 A4 04 14 3 A5 05 15 2 A6 2L 06 16 zi 07 r 1Z 22 A9 g D 11 ROMSO h ti l ri DE vee 5 1 7 HBNKO 2 rtrt 4 _ 171 010Le_ Jj mm 6 1 2 0211 5 A3 03 13 A4 04 14 I 2 2M g 5 32 6 zj 07rll 22 A9 19 10 21 WE 10 BMCSO I 10 VRAM LS245 IJ XOOO SO co 1 r cs244 8 3C qED 19 E1 L 4 IK 1 r ICS32 XOOO C __ r 9 _q1 g 0 __ 12 2P I 1 1 I g 2 b...

Page 215: ...LS37 8 9 SW RFA311 5 2 MW001 vl l4 LS37 S RFA211 5 5 SW RFA11 5 RFA01 5 0 4 1 lS04 2 DL1 TO 5 7V T1 T2 S NDL 100N101H2 T3 100ns T4 12 T5 11 OA SV TS 9 4 LSOO S CS 5 SU 150 330 r 5V 1 33 SG R32 R OA TO 4 DL2 T1 5 T2 S NDLZOON101H2 T31 If i i4 ______3 4LS04 4 200ns TS 9 r OA 7W 2 CS I 330 5V o NIJ 4 Q SG RSO R61 R31 33 10 LSOO 8 _ ASLHO 5 CASOO S V RM9 1 AB002 I if I 9 6U T33 1 v MMWLO 6 12 ll 9 1 I...

Page 216: ...1 I i I 9 1 A0121 1 10 1 A0131 12 1 A0141 13 1 AD151r 1 4 6 MR091 6 MRD81j S MRPH11 l 3R 6 MROA1 6 MROB1 1 _ _ _ _ _ _ 6 MROC1 1 _ _ _ _ _ _ _ I 6 MR001 1 _ _ _ _ _ _ _ 1 6 MROE11 _ _ _ _ _ _ _ _ J 6 MROF1_1 _ _ _ _ _ _ _ _ _ J 11 MRHBO I J 11 17 1 1 AB011 1 AB021 1 AB031 1 AB0411 _ _ _ _ J 1 AB0511 J 1 AB0611 1 1 AB0711 J 1 AB0811 _ _ _ _ _ _ _ _ _ J 1 AB0911 1 AB1011 19 11 13 1 AB1111 _ _ _ _ _ ...

Page 217: ... ro 01 DO I A 416 4 i A 416 4 2 2 2 3V 3U w w s n 6 6 9 9 BIT S BIT 6 3 5 CAS I I I ror oo ro I A 416 4 I A 416 4 2 2 3 3 4V 4U w w 6 n 6 9 2 9 2 BIT 9 BIT 10 3 3 4 C S C S I I ro A 416 4 A 416 4 2 6 2 3 3 5V SU w n 6 n 6 9 2 9 2 BIT 13 BIT 14 3 3 4 C S ro I A 416 4 2 2T 6 9 BIT 3 3 OS l ror oo t A 416 4 2 3 3T w n 6 9 BIT 7 3 5 m 2 ror oo 14 t A 416 4 2 3 4T 6 9 2 BIT 11 3 CAS ror oo A 416 4 2 3 ...

Page 218: ... 1 CLK01 I 2 IOWOO 1 _ 1 2 IOROO 1 _ 1 2 AE371 f I LS 2 4 4 1 4 MMROO I 1 2 MRDOO i 2 MWROO 7 1F 1 BHEOO I i 1 ALE01 1 1 DTRO1 1 _ EO E1 2 TSI11 ff 2r i4I 1 2 AB161 1 1 4 LS244 1 2 AB171 1 1 8 1 2 AB181 I 1G 1 2 AB191 1 EO E1 XOOO I I l 3 AD083 D j r t l 11 APFOO 7 X101 1l HBNKO 311 5V 4 11 136 100430 500 A G9PFBU PCB Circuit Diagram Sheet 7 of 11 ...

Page 219: ... 1t1 E 4 LS367 6 7 7P 11 KRSTOvl 1 R E A D D A T AL _t 1 ____ 5V PBSTBE N_ 14i __ R5 2 _1 1K ___ 1 LS14 8 13 LS04 12 _ I 7J 6J C38 I 2200P 5V DTSTBf NN 12 A 5 1 _ 1K ___ _I1 lS14 10 11 LS04 10 T 7J 37 I 2200P 5V R29 1K C28 O 1U 5V 11 NMI01 1 RM1 5V NWR1 049 13K IRQ01 1 X l IRQ 11 1 Xl l IRQ21 1 CxJ I I RQ51 1 CxJ I lAQ61 1 10 IRQ81 1 IAQ91 1 IRQA1 1 IRQB1 1 IRQC1 1 IRQD1 1 IAQE1 1 DRQ01 2 11 DRQ11...

Page 220: ... 1 A0041 DC PA2 2 08 1 IRQ71 1 1 AD031 1l l III g I O __________ __1 ______________ __ 1 ADOS1 g eTR p lit j t l 21 t3 1 AD061 A i R22 R23 1 AD071 pz _______________l 3 3K 3 3K co 1 AB01 1 eo 1 AB021 eo it MASK 4F eo eo eo Lm Wi eo 2 IOROO I 2 IOWO row 0 21 cs Pe4 22 11 CODA0 24 1 RSTO1 PB7 25 VCC 5V XOOO GND R28 1 LSD4 I LS2 4i 5V 9 h1 i _ IIIHR 1 8 8 102JA 7F W I 7rl l fCN2 17 3 3K LSOO 8 l 4 RS...

Page 221: ... R34 33K R35 56K r 1 C2002 R37 8 2 ICL8212 2 2M 31 CPA 4 C3 o1 7rs r 11 R36 20KT7P C31 T R44 1 K 20P SG FOINP01H470K FOINP01H221K 3 o1990AC CO TP L 2 C1 00 II C2 XTAL Ol 0 STB C J 6C II II ClK 01 fnT M M M M CS 11 I aE 1 4 17 VOO I 5V R59 470 v 9 R27 33K 10 9 C2511m 13 L I 22P XT20 12 TC2611m 32 768 KHz I 22P RV 38 v R21 33K I 1 1S LS367 7P A0001 1 3 5 8 9 A0011 1 3 5 8 9 SG2050 5V OS 1 LSOO 3 2 6...

Page 222: ...GNO PJ g I L510 8 11 I 6K 6J Jill LS138 3 50 Fa 2 F1 51 tF2 1 F3 I 52 F4 FS F6 7 F7 4 EO 7M E1 E2 LS139 48R 3 50 tFO 4AR 2 F1 S1 F2 f l 4CR F3 1 EO 7L 4ER L l j S8W 50 tFa 14 F1 S9W 51 F2 F3 SBW 15 EO 7L S8R v v CTMR1 2 CDMAO 2 CITMO 1 CITSO 1 CTIMO 2 CODAO 9 CDMRO 2 KRDTO 8 KRSTO 8 KRSGO 8 KRBPO 8 WTSDO 10 BMMEO 3 APFOO 7 WTRDO 10 MRHBO S MRLBO S MRDSO 7 ROMSO 3 RAMSO S 7 BMMSO 3 BEXCO S DMACO 3 ...

Page 223: ...4 2 8 9 4 10 L03 2 8 9 4 10 1 C50 f 19 EO L02 2 8 9 4 9 10 L01 2 8 9 4 9 10 LOO 2 8 9 4 9 10 2 AB1 4 2 8 9 AB2 4 10 AB3 4 AB4 4 AB5 4 AB6 4 AB7 4 XOOO 1 LSD 16LB PAL OT R R2I7r 2H BHE R26 IOR R23 IOR1 2 IOW R22 IOW1 2 OMC R21 r_____ _l IORO 1 8 9 10 IOWO 8 9 10 A019 A018 A017 12 A016 1M X111 n XOOO MRO llim HRO 4 MW 11 LS04 LSICS LS138 n n f lIO SELECT 15138 2 Sl n 3J 2 IJACKO ___________ J 8 IlAC...

Page 224: ...6 G080131 GDB4IJI OIlB6 3 GOB10 31 00811 31 0814 31 OA s 18 6 GA89I A 12 r H lol l S IJ 44 A WeRT 10 MS 1 r IT 13 MR GMW113 31 O IORI 1f p 14 2 Celll II 1114 11IX 8 XOOO H TO A WIOWI t 1f 3 8LNI 10141 0 8lNI 20 5 I SI 41 2i 7 15 A81CLC215 14 LOAOO 1llXl11A I 1 v L J 3 12 04 m 3 Go Pi cp 1 30 ID 11 1118 10 MS 10 08 13 MR OA F 111 ADO XODOt ff r G1R I 30 3 111INTRO GO 15 l OACKC ll HI81 riP RST1 8 9...

Page 225: ... 2 GAB11 3 GAB11 2 GMW1 12 LSOO 2 GAB12 3 2 OBIN1 S LSOD 4 MDO 4 L t M01 4 M02 4 M03 4 MD4 4 MDS 4 MD6 4 M07 4 MOS 4 MD9 4 MD10 4 M011 4 MD12 4 MD13 4 M014 4 M01S 4 LS08 3 2 3V 10 II LSOO 8 D449 AO 00 ATTRIBUTE 1 AS 0 A4 o AS OS 2 A6 06 A7 07 I L 22 A 2P A 1 0 VCC 5V CS1 CS2 GNO D449 00 7 AO A1 g 11 S A2 4 AS 0 1 A4 g 1S 2 AS A 1 A7 2R AS A VCC 5V CS1 CO2 GNO 11 LSD8 8 3V 1A S 2A 2 3A 4A 3V 4 SA S...

Page 226: ... 2N 1IlDS IULD4 1 LOJ ULD2 111LDI 1IlDO 3 LS 11 5 13 f I1lAB16 t 141 ANK0II AB15 3B 41M896 M xoooC M896111l Dorcl5 1 ASI7 l fi IHAB1 llMRQ IOMW lL___J I CC4 fil l J CC3 6 rJ I CC1 b n ceoiSi n ce7IS S 11 n ACG 6 n II ANKOIA15 ANK II B l c BVO 5 5 1 LOAD 14 2 5J LOA DO 2 10 OOTeIS 136 100430 501 A G9PFCU PCB Circuit Diagram Sheet 4 of 11 ...

Page 227: ...11 D 1 0 01 J J r t ED R _R mOil nlOBi UlOI l DSJ mrn nlDBI IA mm 41UA XD D ZlllNIlZOi j lIIlU I _ _ _ _ _ _ _ _ _ _ _ 1IIIIEool 161 BlUI V n f 1 1COLOR I GRNO t O etlY u XOIJII f o MONOCHROME 5 BLlNKO SIRVSI I 21 CSR I J l 2 1S 8 t VLOI5 51 5 t E H lIl11118 p t GRNO IS 6J II l j H 4 51 BLUG 5 ff BLU 5 13 IL ll1X 1I8 9 1I x jl RED ItLT1 IS 5J 34 r t COLOR OPEN MONOCHROME SHORT B 19 136 100430 501 ...

Page 228: ...o 5V WE VCC CS1 CS2 GNO l II l II I XlIOBO 1 OB1 1 OB2 1 OB3 1 OB4 1 OB5 1 OB6 1 OB7 1 1 11 I v11 A 1 I v1 A A 1 OB8 1 OB9 1 OB10 1 OB11 1 OB12 1 OB13 1 OB14 1 OB15 1 4 LCA3 V 11 0 A LS 2 44 0 81 68 1l C Ni2 1 4 LCA2 1 NZ 3A 38 4 LCA1 J Nc J 4 LCAO J 4N CN2 4 4 CC15v 1 _ CN2 5 r l EO 4 CC14 t 1 E1 CN2 0 4 CC13 I CN2 7 4 CC12 CN2 8 4 CC11 OA LS244 08 CN29 1A 18 14 4 CC10 Ja CN2 10 KANJI INTERFACE 4...

Page 229: ...7A 78 1 EO 19 E1 X111 4 CC7 2 4 ACG I J 6 2 HSYNC ____ 5v 2 USYNC 1 4 1 14 1 18 16 14 1 5V R33 1K 50 HD R34 5V R29 LK2 50 VD R30 DB15 1 DB14 1 DB13 1 DB12 1 DB11 1 DB10 1 DB9 1 DB8 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DBO 1 XOOO I _I Pin assignment of CRT display unit connector B 21 136 100430 501 A G9PFCU PCB Circuit Diagram Sheet 7 of 11 ...

Page 230: ...E a t ttio 11110WO 1 ABI 19 AD SO f i K ST M 2 RSTI I RST 5VGNDSYNC 1000l Ff C81 1 000 _________________ l tittt l 4 41 39 xooo ___________________ J X I I q IJ j 8 9 06 I lV lS _ If_ _ l 21 I 11 X l L JIO r 1 L S Y L I lOA ZIRSTO I cp L OB M m M n r r ___ 9 R xoooD 136 100430 501 A 5 25 5 23 5 21 5 19 lCT1IB 5 33 5 37 s 27 5 13 G9PFCU PCB CircuIt DIagram Sheet 8 of 11 ...

Page 231: ...S I 3 l 11 A _ _ _ _ I c_ 8 rc l 18 L ______ 4 r C M Jll_ IX r IJ 9 kr8 I 2 C M 2 1 O A 3 L__ 2 CI T o J 8 2 2 CM3 fF 1 TOW 11 I i o 4 4 MS 3C 6 r CP C 4 8 2A T C _ M A f 13 f 8 1I J HT 4 1489 6 9 04 1 10 1 0 1 2 PHI I 2 38 j 7E Xl 1 7f T I 9 RTI 02 1 5V R26 r O 3 XDDO 6 r J 9K n lA tl02 ClOt 2A LS TO 12 T1 13 12 14 12 1314 so LS 51 42 52 53 4 2 f2 LS 3 10 6 f3 4E I 00 30 3 f4 I cm xooo TM2 It lil...

Page 232: ...V C4 C515E1V6R8M 8C C83 CKD1DF1H1a4Z C B 24 GNO L I XDDO 5V 5V 1K 1K R21L X111A 2 2 2 C61 R22L X111B 2 2 4 4 4 C79 5 5 5 5 5 Pin assignment of FDD connector 50 2 0 1U T XOOO t J 0 1U T 9 9 9 9 10 xooo t J DETAIL OF ZR1 JlllllU R 1K DETAIL OF ZR4 DETAIL OF ZR3 5 v l l W l U R 150 Pin assignment of MODEM connector RF07Q102G RF07Q102G RF07Q151G 136 100430 501 A G9PFCU PCB Circuit Diagram Sheet 10 of ...

Page 233: ... INTR 1 2 RSTO 2 WiiO 11 CP I ___________ _________ L 2 23_______ l 04 10 LS74 7L 10 L O 8 ____ 1 L22 5V e89 10U 1 1 e91 O 1U e9 R45 XOOO t 10lUJ 10K 8 18 DO 01 SOUND 02 01771 03 005 04 05 28 PIN 06 07 4 WA eH1 I s 10U _ _ _ _ 3 RO SOUND 1 1 3 vA 17Y rn I l W v IeN6 r 9 l elK v 3 3 K 1 SNDO __________________ ______ 5 es 4X P8 0 1U I i XOOO D __________ _ 6 _lEXINT 5V GND 8 4MHZD l9 1 2 J 1 M5 MA ...

Page 234: ...C 2 to C 5 describes each PAL device in terms of its inputs and outputs Table C l Identification and Location of PAL Devices STAMPED MANUFACTURER IDENTIFICATION DATA PCB LOCATION PFBOIC MMI PAL 16L8 G9PFBU Processor PCB or Location 7N Signetics N 82SI53F PFB02 MMI PAL lOL8 G9PFBU Processor PCB Location IN PFCOI MMI PAL I4L4 G9PFCU Controller PCB or Location 2H Signetics N 82SI53F NMS02 MMI PAL I4L...

Page 235: ...6 A5 BHEO AE3il A7 A6 A5 A4 A3 BHEO AE371 A7 A6 A5 A4 A3 AO AE371 A7 A6 A5 A4 A3 A2 AI AO AE371 A7 A6 A5 A4 A3 A2 AO AE371 A7 A6 A5 A4 A3 BHEO AE371 A7 A6 A5 A4 A3 AO AE371 A7 A6 A5 A4 A3 A2 Al AO AE371 A7 A6 A5 A4 A3 AO AE371 A7 A6 A5 A4 A3 A2 AI AO AE371 A7 A6 A5 A4 A3 A2 BHEO AE371 A7 A6 A5 A4 A3 A2 Al AO AE371 A7 A6 A5 BHEO AE371 A7 A6 A5 A4 AO AE371 A7 A6 A5 A4 A3 BHEO AE371 A7 A6 A4 A3 AO AE...

Page 236: ...DMC 18 RAMS 3 AB19 17 BMMS 4 AB18 16 BEXC 5 AB17 15 MRBS 6 MRD 14 DMA 7 lOR 13 MPR 8 MRQ 12 ITMM 9 ABO 11 IMM ROMS ABI9 ABI8 ABI7 MRD RAMS ABI9 ABI8 AB17 BMMS ABI9 ABI8 ABI7 MRQ BEXC DMC MRQ ABO MRBS ABI9 ABI8 ABI7 MRD DMA DMC IOR DMC MRD ABO IMM MPR DMC MBCS IOR DMC MRD IMM ITMM ABI9 ABI8 ABI7 ABI9 ABI7 C 3 ...

Page 237: ... A6 A5 A4 A3 A2 BHE _ __ A6 A5 A4 A3 A2 AI AO DT R A6 A5 A4 A3 A2 AI AO DT R A6 A5 A4 A3 A2 AI AO A6 A5 A4 A3 A2 AO A6 A5 A4 A3 AI AO A6 A5 A4 A3 A2 BHE A6 A5 A4 A3 A2 BHE __ A6 A5 A4 A3 A2 AI AO DTIR A6 A5 A4 A3 A2 A1 AO DTIR A6 A5 A4 A3 A2 AI AO DT R A6 A5 A4 A3 A2 AO A6 A5 A4 A3 A2 BHE A6 A5iA4 A3 A2 AI AO A6 A5 A4 A3 A2 BHE __ A6 A5 A4 A3 A2 AI AO DTIR A6 A5 A4 A3 A2 AI AO DTIR A6 A5 A4 A3 A2 ...

Page 238: ...O 2 CC6 16 FULLl 3 CC5 15 BEO 4 CC4 14 BSO 5 CC3 6 CC2 7 CC1 8 CCO 9 M8960 11 MRQO 12 MWO 13 XNU 18 XNU 19 XNU ANKO CC7 CC6 CC5 CC4 CC3 CC2 CC1 CCO FULLl CC6 CC5 CC4 CC3 CC2 CC1 CCO CC6 CC5 CC4 CC3 CC2 CC1 CCO CC6 CC5 CC4 CC3 CC2 CC1 CCO CC6 CC5 CC4 CC3 CC2 CC1 CCO BEO M8960 MRQO BSO M8960 MRQO MWO C 5 ...

Page 239: ... 1 The meanings of the ASCII special characters are given in Table 0 2 Table 0 3 lists the APC special characters that differ in representation from the ASCII standard but the generated code is the same A quick reference quide for easy association of the ASCII special characters and APC special characters is provided in Table 0 4 The APC GRPHI characters are shown in Figure 0 1 the GRPH2 character...

Page 240: ... 84 U 85 V 86 W 87 X 88 Y 89 Z 90 91 92 93 1 94 95 FIRST HEX DIGIT 6 7 8 9 A p L 96 112 1144 1160 a q 97 113 161 b r 98 114 _146 1162 c s 99 115 1147 r 1163 d t 100 116 1148 1164 e u 101 117 1149 165 f y 102 118 lli J 166 w 151 I16J g 103 119 h x lml 16 z 104 120 36 i y Q 16J 105 121 137 j z l 106 122 llli 170 k 117 107 123 155 I 108 124 b 172 m 109 125 173 n I 110 126 158 0 DEL 7 III 127 lilll 17...

Page 241: ...a Link Escape DCI Device Control I DC2 Device Control 2 DC3 Device Control 3 DC4 Device Control 4 NAK Negative Acknowledge SYN Synchronous Idle ETB End Transmission Block CAN Cancel EM End of Medium SUB Substitute ESC Escape FS Form Separator GS Group Separator RS Record Separator US Unit Separator SP Space DEL Delete NOTE These codes are not displayed on the APC as shown Some ofthese codes are no...

Page 242: ...1 17 2 02 18 3 III 03 19 4 Z 04 20 5 2J X 05 21 6 OK CD 06 22 7 D 07 23 8 t I 08 24 9 09 25 A 0 10 26 B rn II 27 C El 12 28 D J 13 29 E 0 14 30 F 00 c J 15 31 APC 8 Character Decimal Code NOTE Only characters that are not associated with a specific APe function are displayed on the screen ...

Page 243: ...on ASCII APC SPECIAL SPECIAL CHARACTER CHARACTER NUL SOH STX ETX m EaT z ENQ 2 ACK Ok BEL t BS l HT LF 0 VT FF CR SO SI 00 DLE r J DCI DC2 DC3 DC4 NAK X SYN CD ETB 0 CAN I EM SUB ESC CD FS 0 GS 2J RS D US Ll SP DEL NOTE Characters associated with a specific APe function are not displayed D 5 ...

Page 244: ...WN NOTES 1 GRPHI CHARACTERS ARE PRODUCED WHEN THE GRPHI KEY IS PRESSED 2 GRAPHICS SYMBOLS ASSOCIATED WITH A SPECIFIC APC FUNCTION ARE NOT DISPLAYED ON THE SCREEN INSTEAD THE FUNCTION IS PERFORMED 3 THE ALPHANUMERIC SYMBOLS ASSOCIATED WITH THE GRAPHIC SYMBOLS ARE THE HEXADECIMAL HEX CODES GENERATED BY PRESSING THE KEYS Figure D l APC GRPHI Characters OD lA ...

Page 245: ...IFTED SHIFT KEY UP 0 v EB 0h t t l GRPH2 Character He Code S B SHIF1ED SHIFT KEY DOWN Character on Key Cap irA I NOTE GRPH2 CHARACTERS ARE PRODUCED WHEN THE GRPH2 KEY S PRESSED Figure D 2 APC GRPH2 Characters D 7 ...

Page 246: ...R HEX CODES OF STANDARD ALPHANUMERIC CHARACTERS SEE TABLE D 1 3 KEYS WITH 0 MUST BE USED WITH ANOTHER KEY TO GENERATE A CODE 4 SHIFT OR cTRL PLUS BREAK STOP GENERATES HEX CODE 03 5 KEYS WITH 00 PFI7 TO PF22 GENERATE THE SPECIAL CODES SHOWN BELOW PFI7 ESCOO PFI8 ESCOP PFI9 ESCOQ PF20 ESCOIR PF21 ESCO S PF22 ESCO T FNC PFI7 ESCOIU FNC PFI8 ESCOV FNC PFI9 ESC OW FNC PF20 ESC O X FNC PF21 ESCOY FNC PF...

Page 247: ...structions The I O port addresses and instructions for all devices are listed in Tables E l to E 21 Data bus bit descriptions are listed left to right as Bits 7 through 0 for low order bytes and Bits 15 through 8 for high order bytes E l ...

Page 248: ... CHI Address Write W 03 A7 A6 A5 A4 A3 A2 Al AO AI5 AI4 AI3 AI2 All AlO A9 A8 CHI Word Count R R 13 W7 W6 W5 W4 W3 W2 WI WO WI5 WI4 W13 WI2 WII WlO W9 W8 CHI Word Count W W 13 W7 W6 W5 W4 W3 W2 WI WO WI5 WI4 WI3 WI2 Wll WlO W9 W8 CH2 Address Read R 05 A7 A6 A5 A4 A3 A2 Al AO AI5 AI4 A13 AI2 All AlO A9 A8 CH2 Address Write W 05 A7 A6 A5 A4 A3 A2 Al AO AI5 AI4 A13 AI2 All AlO A9 A8 CH2 Word Count R ...

Page 249: ...2 Wll WlO W9 W8 DMA Status Read R 09 RQ3 RQ2 RQI RQO TC3 TC2 TCI TCO DMA Command W 09 KS DS WS PR TM CE AH MM Write Illegal R 19 Write Request W 19 RB CSI CSO Register Illegal R OB Write Single Mask W OB MK CSI CSO Illegal R IB Write Mode W IB MSI MSO ID AT TRI TRO CSI CSO Illegal R OD Clear F F W OD Read Temporary R ID D7 D6 D5 D4 D3 D2 DI DO Register Master Clear W ID Illegal R OF Illegal W OF I...

Page 250: ... R 22 M6 M5 M4 M3 M2 MI MO OCWI W 22 M6 M5 M4 M3 M2 MI Ma ICW2 W 22 T7 T6 T5 T4 T3 a 0 a ICW3 W 22 I a 0 0 a a a a ICW4 W 22 0 0 0 a a 0 a I R 24 W 24 R 26 W 26 Read IRR ISR IRL R 28 D7 D6 D5 D4 D3 D2 DI DO OCW2 W 28 R SL EOI 0 0 L2 Ll La OCW3 W 28 a ESM SMMO I P PR RIS ICWI W 28 0 0 a I a a 0 I Read Mask R R 2A MI4 M13 MI2 MIl MIO M9 M8 M7 OCWI W 2A M14 M13 MI2 MIl MIO M9 M8 M7 ICW2 W 2A T7 T6 T5...

Page 251: ...6 CS C4 C3 C2 CI CO CIS CI4 CI3 CI2 CII CIO C9 C8 Read Counter I R 2B C7 C6 CS C4 C3 C2 CI CO CIS CI4 Cl3 CI2 Cil CIO C9 C8 Load Counter I W 2B C7 C6 CS C4 C3 C2 CI CO CIS CI4 Cl3 CI2 CII CIO C9 C8 Read Counter 2 R 2D C7 C6 CS C4 C3 C2 CI CO CIS Cl4 CI3 CI2 Cli ClO C9 C8 Load Counter 2 W 2D C7 C6 CS C4 C3 C2 Cl CO CIS CI4 CI3 CI2 CII CIO C9 C8 No Operation R 2F Write Mode W 2F SCI SCO RLI RLO M2 M...

Page 252: ...e Mask W 34 0 0 0 0 0 TXE RXR TXR Read Signal R 34 CS CI CD Write Signal W 36 0 0 0 0 0 0 0 TDC R 36 Table E 5 1 0 Port Addresses and Instructions for the Serial 110 Communications Controller Number 2 READ 110 INSTRUCTION WRITE ADDRESS DATA BUS Read Data R 31 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RDI Write Data W 31 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SDI Read Status R 33 DR SYN FE OE PE TE RRDY TRDY Write Mode A W...

Page 253: ...AI6 CH2 Read Address R 3C CH2 Write Address R W 3C 0 0 0 0 AI9 AI8 AI7 AI6 CH3 Read Address R 3E CH3 Write Address R W 3E 0 0 0 0 AI9 AI8 AI7 A16 Table E 7 1 0 Port Addresses and Instructions for the CRT Controller READ I O INSTRUCTION WRITE ADDRESS DATA BUS Read Status R 40 LP lIP VS DMADW FE FF DR Write Parameter W 40 P7 P6 P5 P4 P3 P2 PI PO Read Data R 42 D7 D6 D5 D4 D3 D2 DI DO Write Command W...

Page 254: ...e E 9 VO Port Addresses and Instructions for the Keyboard Controller READ 110 INSTRUCTION WRITE ADDRESS DATA BUS Read Data R 48 SD8 SD7 SD6 SD5 SD4 SD3 SD2 Buzzer Set W 48 Read Status R 4A TP2 TPI TPO Buzzer Reset W 4A Read Signal R 4C SW8 SW7 SW6 SW5 SW4 SW3 SW2 Read Book Page R 4E B4 B3 B2 Bl P4 P3 P2 Read Shift R 4E 0 0 0 0 SF4 SF3 SF2 Table E IO 1 0 Port Addresses and Instructions for the FDD ...

Page 255: ...INSTRUCTION WRITE ADDRESS DATA BUS BBM Enable W 59 ENB Table E 13 I O Port Addresses and Instructions for the APU READ I O INSTRUCTION WRITE ADDRESS DATA BUS Read Data R 5A 07 06 05 04 03 02 01 DO Write Data W 5A 07 06 05 04 03 02 01 DO Read Status R 5E B S Z E3 E2 El EO CRY Write Command W 5E C7 C6 C5 C4 C3 C2 Cl CO Table E 14 I O Port Address and Instruction for the Power Off Control READ I O IN...

Page 256: ...ead Status R 60 S7 S6 S5 S4 S3 S2 Sl SO Table E 16 I O Port Addresses and Instructions for the Timer READ I O INSTRUCTION WRITE ADDRESS DATA BUS Read Counter 0 R 61 C7 C6 C5 C4 C3 C2 Cl CO Cl5 Cl4 Cl3 Cl2 CII CIO C9 C8 Load Counter 0 W 61 C7 C6 C5 C4 C3 C2 CI CO CI5 CI4 CI3 CI2 CII CIO C9 C8 63 63 65 65 67 Write Mode W 67 SCI SCO RLI RLO M2 MI MO BCD E lO ...

Page 257: ...l 1 W 6E 0 0 0 0 1 0 0 MASK Write Signal 1 W 6E 0 0 0 0 1 1 1 IRT Table E 18 1 0 Port Addresses and Instructions for the IDA Controller READ 110 INSTRUCTION WRITE ADDRESS DATA BUS Read Signal R 71 DCN IP3 IP2 PSM SMR IPI SDRQSTT Read Data R 73 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SDI Write Signal 2 W 75 IRT SDR SMS MASK Write Signal 0 W 77 1 0 0 1 0 1 1 0 Write Signal 1 W 77 0 0 0 0 0 1 0 INTE Write Signal...

Page 258: ...7 D6 D5 D4 D3 D2 DI DO Read BUF6 R 84 D7 D6 D5 D4 D3 D2 DI DO Start DMA W 86 Set INTI W 88 Reset INT2 W 8A Reset SDMA INT W 8C Reset RDMA INT W 8E Read INT R 90 INTI INT2 MSDE MRDE Table E 20 I O Port Addresses and Instructions for the ASOP Controller READ 110 INSTRUCTION WRITE ADDRESS DATA BUS Low Address Set W FO SA7 SA6 SA5 SA4 SA3 SA2 SAl SAO Mid Address Set W F2 SAl5 SAl4 SA13 SAl2 SAll SAlO ...

Page 259: ...tstrap and self test 64K chips 200 ns Access Time 128 KB 256 KB 4 K CMOS Two year life Can be protected against accidental writing Parallel Asynchronous and Synchronous at speeds up to 19 200 bps Software Emulators for all important IBM Workstations and Communications subsystems Second RS 232C Port Pitch Range 2 Octaves Number of Tempos 4 Note Duration thirty second to whole Dynamics piano medium ...

Page 260: ... Phosphor Type Video Interface Color Virtual Graphic Area Size Real Graphic Window Size SPECIFICAnON Pitch 4 selectable frequencies Length 20 ms or continuous Loudness 3 levels Hardware with battery backup Can be initiated locally or remotely Backs up CMOS RAM and Clock Calendar Two year life Integrated one or two 8 in 243 KB 1 MB Both supported monochrome model one color model two two 2MB 360 rpm...

Page 261: ...Enclosure Keyboard SPECIFICATION Overline underline vertical line highlight inverse video blinking secret Line segment rectangle arc circle 86 22 Dual Mode effectively 44 Standard Dot Matrix 100 Characters per second Standard 19 7 in 50 cm wide x 13 8 in 35 cm high x monochrome 18 1 in 46 cm deep color 19 9 in 50 5 cm deep 19 7 in 50 cm wide x 2 4 in 6 cm high x 9 1 in 23 cm deep Standard Feature ...

Page 262: ...lse ANSI American National Standards Institute an organization that develops and publishes industry standards including terminology and standard codes APC Advanced Personal Computer ASCII American Standard Code for Information Interchange this standard defines character set codes that are used for data interchange between equipment of different manufacturers This code defines 96 displayed characte...

Page 263: ...r second in a train of binary signals and one 3 bit value per second in a train of signals each ofwhich can assume one ofeight different states 2 In asynchronous transmission the baud is a unit of modula tion rate that equals the unit intervals BBM Battery Backed Memory BHE Bus High Enable a bus interface channel See Chapter 2 Binary 1 A condition that can have exactly two values for example ON an...

Page 264: ...Chip A tiny piece of semiconductor material on which microscopic electronic components are photoetched to form one or more circuits After connector leads and a case are added it is called an integrated circuit CLKO Communications Clock a bus interface channel See Chapter 2 COBOL Common Business Oriented Language a business data processing language Clock 1 The basic source of synchronizing signals ...

Page 265: ...ions CP M is thus a standard interface between user programs and system hardware Among the high level languages that currently run with CP M are BASIC COBOL FORTRAN Pascal APL and PL I CRT Cathode Ray Tube a vacuum tube in which electrons are accelerated to and focused upon a fluorescent screen CRT Display Unit In the APC the equipment that receives data and transforms it into visible images on th...

Page 266: ...ch display unit holds one character box The APC video display has 25 lines of80 display positions and each display position is composed of an 8 x 19 dot matrix DMA Direct Memory Access high speed data transfer operation in which an I O channel transfers information directly to or from the memory Transfers take place with no microprocessor intervention using a cycle stealing method Also called data...

Page 267: ...ecify the status of a designated condition A flag is usually one or two bits and can be hardware or software implemented Floating Point Arithmetic Arithmetic procedures in which the computer keeps track of the radix point Compare fixed point arithmetic FM Frequency Modulation Full Duplex In communications pertains to simultaneous two way independent transmission in both directions also called dupl...

Page 268: ...o or receive data from a computer Integrated Circuit IC A microunit consistmg of interconnected elements inseparably associated and formed on or within a single substrate to function as an electronic circuit Intel A large semiconductor designer manufacturer and distributor Interlace To assign successive storage location numbers to physically separate storage locations this reduces access time Inte...

Page 269: ...ard to memory space and addressing mega means 1 048 576 2 to the 20th power for example one MB equals one megabyte 1 048 576 bytes Machine Language Binary coded language the only type of language that can be directly used by the machine Main Unit In the APe the Main Unit houses all the microcomputer devices except the Keyboard and Printer In addition all interfaces are in or on this unit Matrix Pr...

Page 270: ...d verifies the operation ofa data processing system and indicates any significant departure from the norm 2 Software or hardware that observes supervises controls or verifies the operation of a system 3 A video display MOS Metal Oxide Semiconductor Mother Board A circuit board into which various printed circuit boards PCB are plugged In the APC the Mother Board is inside the card cage and has five...

Page 271: ... P Q Output Pertaining to a device process or channel involved in an output process or to the data or states involved in an output process Overflow That portion of the result of an operation that exceeds the capacity of the intended unit of storage Parallel Data Method for representing data in which characters are transmitted and received over separate lines usually simultaneously Compare serial d...

Page 272: ...y where the AND is programmable and the OR fixed PALs are used to make logic modification quicker and easier than with standard devices PROM Programmable Read Only Memory unprogrammed upon manufacture can be programmed once and only once After programming like ROMs they retain their contents indefinitely Protocol In data communications a specific set of rules defining the format and content of mes...

Page 273: ... NEC 8251 A Communications Controller See Chapter 3 Serial Data Method for representing data in which the data stream is transmitted and received as a single signal by single transmission path Compare parallel data Single Density Refers to a magnetic disk storage technique in which 128 charac ters ofinformation are stored on each sector ofa track Compare double density Software A set of programs p...

Page 274: ...e number ofcharacters is preceded by one or two sync bits which indicate where the data stream begins TC Terminal Count a bus interface channel See Chapter 2 TTL Transistor Transistor Logic USART Universal Synchronous Asynchronous Receiver Transmitter V Abbreviation for Volt VFO Variable Frequency Oscillator W Abbreviation for Watt Word A group ofcharacters that occupy one storage location and are...

Page 275: ...vements to this manual Please list any errors in this manual Specify by page From Name __________________________________________________________________ Title _____________________________________________________________ Company ______________________________________________________________ Address _________________________________________________________ Dealer Name _____________________________...

Page 276: ... CARD FIRST CLASS PERMIT NO 386 LEXINGTON MA POSTAGE WILL BE PAID BY ADDRESSEE NEe Information Systems Inc Dept Publications APC 5 Militia Drive Lexington MA 02173 FOLD HERE Seal or tape ali edges lor mailing do not use staples NO POSTAGE NECE S SARY IF MAILED IN THE UNITFD STATES ...

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