Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
RDES3 has 2 functions: when data is received, the address of buffer 2 or the address of next descriptor and the high
32-bit timestamp are stored. Before DMA controller obtains the descriptor, if RDES1.RCH = 0, configure RDES3 as
the address of buffer 2. At this time, if RDES1.RBS1 is not 0, use the address of RDES3 to store the received data
frame; if RDES1.RCH = 1, then configure RDES3 as the next descriptor address, and the address needs to be word-
aligned. If RDES1.RER is not 0, then RDES3 is ignored.
When timestamp function is enabled and RDES0.LS is 1, if the received frame passes the address filtering and the
corresponding frame type enable bit is set, DMA will write the high 32 bits of the timestamp to RDES3. If the
corresponding frame type enable bit is not set in the received frame, RDES3 will keep the value of the original address.
25.4.8.4.3 Processing when a new frame is received in suspended state
In suspended state, when a new frame is received and the forwarding conditions are met, RxDMA will obtain the
frame descriptor. If RDES0.OWN is 1, RxDMA controller exits the suspend state and resumes the running state to
start receiving frames. But when RDES0.OWN is 0, application can choose whether to clear the frame in RxFIFO
by configuring ETH_DMAOPMOD.DFF. If ETH_DMAOPMOD.DFF = 0, RxDMA controller will drop the current
frame at the top of RxFIFO and increment ETH_DMAMFBOCNT.MISFRMCNT (missed frame count) by 1 (repeat
the process if there is more than one frame in RxFIFO). If ETH_DMAOPMOD.DFF = 1, the frame at the top of
RxFIFO will not be dropped. When RDES0.OWN is 0, ETH_DMASTS.RU bit will be set and RxDMA controller is
still suspended.
25.4.8.4.4 Get receive descriptor
DMA will attempt to acquire a receive descriptor whenever any of the following conditions are met:

ETH_DMAOPMOD.SR changes from 0 to 1, when DMA controller enters the running state

Before EOF is received, the buffer of current descriptor is full, and the entire buffer of current descriptor is not
large enough to receive the entire frame

A complete frame is received and forwarded to receive buffer, but current descriptor has not been closed

A new frame is received when DMA is suspended without occupying the descriptor

Perform any write operation to ETH_DMARXPD register
25.4.8.4.5 RxDMA operation flow
The operation flow of RxDMA is as follows:
1. Initialize DMA receive descriptor and set RDES0.OWN to 1;
2. Set ETH_DMAOPMOD.SR bit to 1 to enable RxDMA controller. After DMA enters running state, receive
descriptor is obtained from the base address of the descriptor list configured by ETH_DMARXDLADDR
register. If RDES0.OWN is 1, the current descriptor starts to receive frames; if RDES0.OWN is 0, DMA enters
suspended state and skips to step 9;
3. If the obtained descriptor shows that the descriptor is occupied DMA (RDES0.OWN = 1), then the control bit
and cache address of the descriptor will be parsed and recorded by DMA;
4. Process the received frame and transfer the data from RxFIFO to receive buffer;
5. If frame transfer is complete or buffer is full, receiving controller will get next receive descriptor from descriptor
queue;