Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
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+86-755-86309900
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info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
register, and the relevant bits of the ETH_MACMIIADDR register need to be operated:
1. Set device address and specific register address of the PHY to be operated, and set ETH_MACMIIADDR.MW
to 1 to enable the write mode;
2. Set ETH_MACMIIADDR.MB to 1 to start transmission. The ETH_MACMIIADDR.MB bit can be used to
judge whether the transmission is completed. During the transmission process, the ETH_MACMIIADDR.MB
bit is always high until the transmission is completed, and the hardware will automatically clear the
ETH_MACMIIADDR.MB bit. When the ETH_MACMIIADDR.MB bit is 1, modifying the contents of
ETH_MACMIIADDR and ETH_MACMIIDAT will be invalid.
SMI read operation
To implement the SMI read operation, it is necessary to operate the relevant bits of the ETH_MACMIIADDR register:
1. Set device address and specific register address of the PHY to be operated, and set ETH_MACMIIADDR.MW
to 0 to enable the read mode;
2. Set ETH_MACMIIADDR.MB to 1 to start receiving data. The ETH_MACMIIADDR.MB bit can be used to
judge whether the transmission is completed. When receiving data, the ETH_MACMIIADDR.MB bit is always
high. After the reception is completed, the hardware will automatically clear the ETH_MACMIIADDR.MB bit.
When the ETH_MACMIIADDR.MB bit is 1, modifying the contents of ETH_MACMIIADDR and
ETH_MACMIIDAT will be invalid.
Note: The contents of the PHY registers with addresses 16-31 are customized by the manufacturer, so you need to
make corresponding settings according to the PHY device manual to access this part of the registers.
SMI clock configuration
The clock of SMI interface is derived from AHB clock frequency division. Set the ETH_MACMIIADDR.CR[2:0]
bits according to the AHB clock frequency, configure the appropriate frequency division factor, and ensure that the
MDC clock frequency does not exceed 2.5MHz.
The SMI clock configuration ranges are as follows:
Table 25-2 SMI clock configuration range
ETH_MACMIIADDR.CR[2:0]
value
MDC frequency HCLK frequency
000 HCLK/42 60~100MHz
001 HCLK/62 100~144MHz
010 HCLK/16 20~35MHz
011 HCLK/26 35~60MHz
25.4.4 MII interface
MII is used for MAC and external PHY interconnection, and supports 10Mbps and 100Mbps data rate transmission
modes.