Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 21-25 I
2
S clock generator structure
Note: The clock source of I
2
Sx CLK is HSI, HSE or PLL system clock that drives AHB clock.
The bit rate of I2S determines the data flow on the I2S data line and the frequency of the I2S clock signal.
I
2
S bit rate = number of bits per channel × number of channels × audio sampling frequency
For a signal with left and right channels and 16-bit audio, the I2S bit rate is calculated as:
I
2
S bit rate = 16 × 2 × F
S
If the packet length is 32 bits, there are:
I
2
S bit rate = 32 × 2 × F
S
Figure 21-26 Audio sampling frequency definition
The sampling signal frequency of the audio can be set by setting the SPI_I2SPREDIV.ODD_EVEN bit and the
SPI_I2SPREDIV.LDIV[7:0] bits. Audio can be sampled at 96kHz, 48kHz, 44.1kHz, 32kHz, 22.05kHz, 16kHz,
11.025kHz, or 8kHz (or any value within this range). Set the linear divider according to the following formula:
When MCLKOEN = 1 and CHBITS= 0,
𝐹
𝑆
= 𝐼
2
𝑆𝑥 𝐶𝐿𝐾 [(16 × 2) × ((2 × 𝐿𝐷𝐼𝑉) + 𝑂𝐷𝐷_𝐸𝑉𝐸𝑁) × 8] ⁄
When MCLKOEN = 1 and CHBITS = 1,
𝐹
𝑆
= 𝐼
2
𝑆𝑥 𝐶𝐿𝐾 [(32 × 2) × ((2 × 𝐿𝐷𝐼𝑉) + 𝑂𝐷𝐷_𝐸𝑉𝐸𝑁) × 4] ⁄
When MCLKOEN = 0 and CHBITS = 0,
𝐹
𝑆
= 𝐼
2
𝑆𝑥 𝐶𝐿𝐾 [(16 × 2) × ((2 × 𝐿𝐷𝐼𝑉) + 𝑂𝐷𝐷_𝐸𝑉𝐸𝑁)] ⁄
When MCLKOEN = 0 and CHBITS = 1,
𝐹
𝑆
= 𝐼
2
𝑆𝑥 𝐶𝐿𝐾 [(32 × 2) × ((2 × 𝐿𝐷𝐼𝑉) + 𝑂𝐷𝐷_𝐸𝑉𝐸𝑁)]
⁄
The exact audio frequency can be obtained by referring to the clock configuration in the table below.
- - - - - -
MOD
SEL
I2SEN
MCLK
OEN
ODD_
EVEN
LDIV[7:0]
0
1
0
1
Divider
by 4
8-bit Linear
D
reshaping
stage
MCLKOEN
CLK
MCLK
I2Sx CLK
Divider
by 2
16-bit or 32-bit right channel 16-bit or 32-bit left channel
32-bit or 64-bit
Fs
：
Audio sampling frequency
Sampling point
Sampling point