Nations N32G45 Series, User Manual

Page: 491 / 838

491 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit Field Name Description
22 SDIOINT SDIO interrupt received.
21 RDATVALID Data available in receive FIFO.
20 TDATVALID Data available in transmit FIFO.
19 RFIFOE Receive FIFO empty.
18 TFIFOE Transmit FIFO empty.
If hardware flow control is used, the TFIFOE signal becomes active when the FIFO contains 2
words.
17 RFIFOF Receive FIFO full.
If hardware flow control is used, the RFIFOF signal becomes active when the FIFO is still 2
words full.
16 TFIFOF Transmit FIFO full.
15 RFIFOHF Receive FIFO half full:
There are at least 8 words left in the FIFO.
14 TFIFOHE Transmit FIFO half empty:
At least 8 more words can be written to the FIFO.
13 RXRUN Data receive in progress.
12 TXRUN Data transmit in progress.
11 CMDRUN Command transfer in progress.
10 DATBLKEND Data block sent/received (CRC check passed).
9 SBERR Start bit not detected on all data signals in wide bus mode.
8 DATEND Data end (Data counter, SDIDCOUNT, is zero).
7 CMDSEND Command sent (no response required).
6 CMDRESPRECV Command response (CRC check passed).
5 RXORERR Received FIFO overrun error.
4 TXURERR Transmit FIFO underrun error.
3 DATTIMEOUT Data timeout.
2 CMDTIMEOUT Command response timeout.
The command timeout is a fixed value of 64 SDIO_CLK clock cycles.
1 DCRCERR Data block sent/received (CRC check failed).
0 CCRCERR Command response received (CRC check failed).
18.7.13 SDIO interrupt clear register (SDIO_INTCLR)
Address offset: 0x38
Reset value: 0x0000 0000
SDIO_INTCLR is a write-only register, writing '1' in the corresponding register bit will clear the corresponding bit
in the SDIO_STS status register.