248
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 10-3 Data format for DAC sync output
10.3.4
DAC trigger
Configure DAC_CTRL. TEN = 1 enables the external trigger of the DAC, and DAC_CTRL.TxSEL [2:0] is
configured to select an external triggering event as the external triggering source for the DAC.
Table 10-2 DAC external trigger
Trigger source
Type
TSEL[2:0]
Timer 6 TRGO events
Internal signal
from the on-
chip timer
000
Timer 8 TRGO events
001
Timer 7 TRGO events
010
Timer 5 TRGO events
011
Timer 2 TRGO events
100
Timer 4 TRGO events
101
EXTI line 9
External pins
110
SWTRIG (Software Triggered)
Software
control bit
111
When the DAC is triggered by timer output or the rising edge of EXTI line 9, when triggered, the data in the aligned
data hold register will be transferred to the DAC_DATOx register. This data transfer process takes 3 APB1 clock
cycles.
12-bit left aligned
31
7
0
31
15
0
8-bit right aligned
31
11
0
12-bit right aligned
15
Master ADC
Slave ADC
16
27
20
4
