Nations N32G45 Series, User Manual

Page: 189 / 838

189 / 838
Nations Technologies Inc.
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+86-755-86309900
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info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
8.4.9 Error management
DMA access to a reserved address area will cause DMA transmission errors. When an error occurs, the transfer error
flag is set, and the hardware automatically clears the current DMA channel enable bit (DMA_CHCFGx.CHEN), and
the channel operation is stopped. If the transfer error interrupt enable bit is set in the DMA_CHCFGx register, an
interrupt will be generated.
8.4.10 Interrupt

Transfer complete interrupt:
An interrupt is generated when channel data transfer is complete. Interrupt is a level signal. Each channel has
its dedicated interrupt, interrupt mask control and interrupt status bit. interrupt status bit is cleared when interrupt
flag clear bit is set.

Half transfer interrupt:
An interrupt is generated when half of the channel data is transferred. Interrupt is a level signal. Each channel
has its dedicated interrupt, interrupt mask control and interrupt status bit. interrupt status bit is cleared when
interrupt flag clear bit is set.

Transfer error interrupt:
An interrupt is generated when bus returned error. Interrupt is a level signal. Each channel has its dedicated
interrupt, interrupt mask control and interrupt status bit. interrupt status bit is cleared when interrupt flag clear
bit is set.
Table 8-3 DMA interrupt request
Interrupt event Event flag bit Enable control bit
Half transfer HTXF HTXIE
Transfer complete TXCF TXCIE
Transfer error ERRF ERRIE
8.4.11 DMA request mapping
DMA1 controller
The DMA1 request mapping is shown in the following figure. By configuring the registers of the corresponding
peripherals, the DMA requests of each peripheral can be turned on or off independently, and according to the channel
priority, only one request is valid at the same time.