Glossary
VXIpc 700 Series User Manual
G-2
©
National Instruments Corporation
backplane
An assembly, typically a printed circuit board, with 96-pin connectors and
signal paths that bus the connector pins. A C-size VXIbus system will have
two sets of bused connectors called J1 and J2. A D-size VXIbus system will
have three sets of bused connectors called J1, J2, and J3.
BERR*
Bus error signal
BIOS
Basic Input/Output System. BIOS functions are the fundamental level
of any PC or compatible computer. BIOS functions embody the basic
operations needed for successful use of the computer’s hardware resources.
bus error
An error that signals failed access to an address. Bus errors occur with
low-level accesses to memory and usually involve hardware with bus
mapping capabilities. For example, nonexistent memory, a nonexistent
register, or an incorrect device access can cause a bus error.
C
CLK10
A 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
CMOS
Complementary Metal Oxide Semiconductor; a process used in making
chips
D
DIN
Deutsches Institut für Normung—German Standards Institute
DMA
Direct Memory Access; a method by which data is transferred between
devices and internal memory without intervention of the central processing
unit
DRAM
Dynamic RAM (Random Access Memory); storage that the computer must
refresh at frequent intervals
Summary of Contents for VXIpc-745-100
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