© National Instruments
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B-5
Internal Timing
AI Timing Clocks
The analog input timing engine has two levels of timing that control an AI acquisition. The first
level is the convert level. This is the timing that controls when the analog to digital conversions
take place. The SC, DIV, and SI2 counters run on this timing level. The signal that clocks this
timing level is called Convert Clock Timebase. This signal can come from an internal source (for
example, an internal timebase) or an external signal. It can be divided down using the SI2
counter, or it can be used directly (in external convert mode). In order to synchronize triggers to
the Convert Clock Timebase signal, another related signal is generated called Sync Convert
Clock Timebase. Sync Convert Clock Timebase is generated differently depending on the mode
the AI timing engine is operating on:
•
When Convert Clock Timebase is a signal that is divided down using the SI2 counter (either
internal or external), it is considered to be a free-running clock. In this case, the Sync
Convert Clock Timebase is the inverted version of the Convert Clock Timebase signal. The
idea is to use the falling edge of the original signal to synchronize external signals before
the rising edge of the Convert Clock Timebase occurs (after polarity selection). This case
is the one described in this section.
•
When Convert Clock Timebase is not going to be divided by the SI2 counter (in the case of
an external convert signal), this signal is assumed to be not free-running and highly
irregular. In this case, Sync Convert Clock Timebase is selected to be the actual external
signal, and Convert Clock Timebase is a delayed version of the external signal. This delay
is long enough so that external signals can be synchronized with Sync Convert Clock
Timebase and used by Convert Clock Timebase. For timing diagrams and parameters for
this case, refer to the
section.
The second level of timing is the sample level. Basically, converts are grouped in sets called
samples, and the timing of the samples can be independent from the timing of the converts. The
M Series device can use a timebase to generate the sample timing. This timebase is called
Sample Clock Timebase. This signal can be internal (for example, an internal timebase) or
external. Either way, the signal gets divided in the SI counter and used to generate Sample Clock
signals (which in turn, signal the start of a sample). In order to synchronize external triggers to
the Sample Clock Timebase, another related signal is created, Sync Sample Clock Timebase.
This is always the inverted signal selected to be Sample Clock Timebase, while the Sample
Clock Timebase signal is a copy without inversion of the signal. The idea is that for each
significant edge of the Sample Clock Timebase, there is a significant edge of the Sync Sample
Clock Timebase signal that occurs before Sample Clock Timebase and that can be used to
synchronize the input triggers.
The source for Convert Clock Timebase and Sample Clock Timebase is the internal signal bus,
_i. The timing of this signal is described in relation to this common point. The Convert Clock
Timebase and Sample Clock Timebase can be asynchronous from each other.
Summary of Contents for PXI-6289
Page 1: ...PXI 6289...
