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9-7
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AO Start Trigger (ao/StartTrigger)
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AO Sample Clock (ao/SampleClock)
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AO Sample Clock Timebase (ao/SampleClockTimebase)
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AO Pause Trigger (ao/PauseTrigger)
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Counter input signals for all counters—Source, Gate, Aux, HW_Arm, A, B, or Z
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DI Sample Clock (di/SampleClock)
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DI Start Trigger (di/StartTrigger)
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DI Pause Trigger (di/PauseTrigger)
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DI Reference Trigger (di/ReferenceTrigger)
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DO Sample Clock (do/SampleClock)
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DO Sample Clock Timebase (do/SampleClockTimebase)
Most functions allow you to configure the polarity of RTSI inputs and whether the input is edge
or level sensitive.
RTSI Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal.
Refer to the
section of Chapter 8,
, for more information.
PXI and PXI Express Clock and Trigger Signals
PXI and PXI Express clock and trigger signals are only available on PXI Express devices.
PXIe_CLK100
PXIe_CLK100 is a common low-skew 100 MHz reference clock for synchronization of multiple
modules in a PXI Express measurement or control system. The PXIe backplane is responsible
for generating PXIe_CLK100 independently to each peripheral slot in a PXI Express chassis.
For more information, refer to the
PXI Express Specification
at
www.pxisa.org
.
PXIe_SYNC100
PXIe_SYNC100 is a common low-skew 10 MHz reference clock with a 10% duty cycle for
synchronization of multiple modules in a PXI Express measurement or control system. This
signal is used to accurately synchronize modules using PXIe_CLK100 along with those using
PXI_CLK10. The PXI Express backplane is responsible for generating PXIe_SYNC100
independently to each peripheral slot in a PXI Express chassis. For more information, refer to
the
PXI Express Specification
at
www.pxisa.org
.
Summary of Contents for PCIe-6323
Page 1: ...PCIe 6323...
