© National Instruments
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9-3
Caution
Do
not
disconnect an external reference clock once the devices have been
synchronized or are used by a task. Doing so may cause the device to go into an
unknown state. Make sure that all tasks using a reference clock are stopped before
disconnecting it.
Enabling or disabling the PLL through the use of a reference clock affects the clock
distribution to all subsystems. For this reason, the PLL can only be enabled or
disabled when no other tasks are running in any of the device subsystems.
10 MHz Reference Clock
The 10 MHz reference clock can be used to synchronize other devices to your X Series device.
The 10 MHz reference clock can be routed to the RTSI <0..7> or PFI <0..15> terminals. Other
devices connected to the RTSI bus can use this signal as a clock input.
The 10 MHz reference clock is generated by dividing down the onboard oscillator.
Synchronizing Multiple Devices
The following sections contain information about synchronizing multiple X Series devices.
PXI Express Devices
On PXI Express systems, you can synchronize devices to PXIe_CLK100. In this application, the
PXI Express chassis acts as the initiator. Each PXI Express module routes PXIe_CLK100 to its
external reference clock.
Another option in PXI Express systems is to use PXI_STAR. The Star Trigger controller device
acts as the initiator and drives PXI_STAR with a clock signal. Each target device routes
PXI_STAR to its external reference clock.
Note
(NI PXIe-6386/6396 Devices)
PXIe-6386 and PXIe-6396 devices differ in
several ways from other SMIO devices. For more information about these devices
related to synchronization, go to
ni.com/info
and enter the Info Code
smio14ms
.
PCI Express Devices
With the RTSI and PFI buses and the routing capabilities of X Series PCI Express devices, there
are several ways to synchronize multiple devices depending on your application.
To synchronize multiple devices to a common timebase, choose one device—the initiator—to
generate the timebase. The initiator device routes its 10 MHz reference clock to one of the
RTSI <0..7> or PFI <0..15> signals.
All devices (including the initiator device) receive the 10 MHz reference clock from RTSI or
PFI. This signal becomes the external reference clock. A PLL on each device generates the
internal timebases synchronous to the external reference clock.
Summary of Contents for PCIe-6323
Page 1: ...PCIe 6323...
