©
National Instruments Corporation
2-1
NI PCIe-1433 User Manual and Specifications
2
Hardware Overview
This chapter provides an overview of NI 1433 hardware functionality and
explains the operations of the functional units on the device.
Functional Overview
The NI 1433 features a flexible, high-speed data path optimized for
receiving and formatting video data from Camera Link cameras.
The following block diagram illustrates the key functional components of
the NI 1433.
Figure 2-1.
NI 1433 Block Diagram
Host Bus
Serial Control
26-Pin MDR Connector
26-Pin MDR Connector
Medium
Configuration
Receiver
Full
Configuration
Receiver
Multiple Tap
Data Formatter
Advanced
Timing
Acquisition,
Region of
Interest, and
Triggering
Camera Control
Base
Configuration
Receiver
UART
Serial Control
Pixel
Clock
Enables
Data
Pixel
Clock
Enables
Data
Pixel
Clock
Enables
Data
Host
Interface
and
Scatter-Gather
DMA
Controllers
50-Pin
I/O Extension
Board
Connector
SMB
Trigger
Connector
34-Pin
RTSI
Connector
