©
National Instruments Corporation
5-1
PCI-DIO-96 User Manual
Chapter
5
Register Map and
Description
This chapter describes in detail the address and function of each
PCI-DIO-96 register.
Note:
If you plan to use a programming software package such as
ComponentWorks, LabVIEW, LabWindows/CVI, or NI-DAQ with your
PCI-DIO-96 board, you need not read this chapter.
Introduction
The three 8-bit ports of the 82C55A are divided into two groups of 12
signals: group A and group B. One 8-bit control word selects the mode
of operation for each group. The group A control bits configure port A
(A<7..0>) and the upper 4 bits (nibble) of port C (C<7..4>). The
group B control bits configure port B (B<7..0>) and the lower nibble of
port C (C<3..0>). These configuration bits are defined in the section
Register Description for the 82C55A later in this chapter. Because there
are four 82C55A PPI devices on the board, they are referenced as
PPI A, PPI B, PPI C, and PPI D when differentiation is required.
The three 16-bit counters of the 82C53 are accessed through individual
data ports and controlled by one 8-bit control word. The control word
selects how the counter data ports are accessed and what mode the
counter uses. The configuration bits are defined in the section Register
Description for the 82C53 later in this chapter.
In addition to the 82C55A and 82C53 devices, there are two registers
that select which onboard signals are capable of generating interrupts.
There are two interrupt signals from each of the four 82C55A devices
and two interrupt signals from the 82C53 device. Individual enable bits
select which of these 10 signals can generate interrupts. Also, a master
enable signal determines whether the board can actually send a request
to the computer. The configuration bits for these registers are defined
in the section Register Description for the Interrupt Control Registers
later in this chapter.
