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Appendix B

Register-Level Programming — Interrupt Control Register 1

©

National Instruments Corporation

B-11

PCI-DIO-96/PXI-6508/PCI-6503 User Manual

5

CIRQ1

PPI C Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI C does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.

4

CIRQ0

PPI C Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI C does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.

3

BIRQ1

PPI B Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI B does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.

2

BIRQ0

PPI B Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI B does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.

1

AIRQ1

PPI A Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI A does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.

0

AIRQ0

PPI A Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI A does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.

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Summary of Contents for PCI-6503

Page 1: ...DAQ PCI DIO 96 PXI 6508 PCI 6503 User Manual 96 Bit and 24 Bit Parallel Digital I O Interface for PCI PXI and CompactPCI PCI DIO 96 PXI 6508 PCI 6503 User Manual March 2009 374938B 01 ...

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Page 3: ...g recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of others and we ask our users to do the same NI software is protected by copyright and other intellectual property laws Where NI software may be used to reproduce software or other ma...

Page 4: ...Installing Other Software 2 1 Hardware Installation 2 1 Installing the PCI DIO 96 or PCI 6503 2 1 Installing the PXI 6508 2 2 Board Configuration 2 2 Chapter 3 Signal Connections I O Connector PCI DIO 96 PXI 6508 3 1 I O Connector Pin Assignments 3 1 Cable Assembly Connectors 3 3 I O Connector Signal Descriptions 3 4 I O Connector PCI 6503 3 6 PCI 6503 I O Connector Pin Descriptions 3 6 Port C Pin...

Page 5: ... Descriptions B 6 Register Description Format B 6 Register Description for the 82C55A B 6 Register Description for the 82C53 PCI DIO 96 PXI 6508 Only B 9 Register Description for the Interrupt Control Registers B 10 Interrupt Control Register 1 B 10 Interrupt Control Register 2 B 12 Interrupt Clear Register PCI DIO 96 PXI 6508 Only B 13 Programming B 14 PCl Local Bus B 14 Programming Examples B 14...

Page 6: ... External Load 3 11 Figure 3 6 DIO Channel Configured for Low DIO Power up State with External Load 3 12 Figure 4 1 PCI DIO 96 PXI 6508 Block Diagram 4 2 Figure 4 2 Timing Specifications for Mode 1 Input Transfer 4 5 Figure 4 3 Timing Specifications for Mode 1 Output Transfer 4 6 Figure 4 4 Timing Specifications for Mode 2 Bidirectional Transfer 4 7 Figure B 1 Interrupt Control Circuitry Block Dia...

Page 7: ...e 3 1 Signal Descriptions for PCI DIO 96 and PXI 6508 I O Connectors 3 4 Table 3 2 PCI 6503 Signal Descriptions 3 7 Table 3 3 Port C Signal Assignments 3 8 Table 4 1 The 82C55A Chips Used in the PCI DIO 96 PXI 6508 and PCI 6503 4 3 Table 4 2 Signal Names Used in Timing Diagrams 4 4 Table B 1 Register Address Map B 5 Table B 2 Port C Set Reset Control Words B 8 Table B 3 Common Programming Example ...

Page 8: ...ts that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example AO 3 0 The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box This icon to the left of bold it...

Page 9: ...ual Field Wiring and Noise Considerations for Analog Signals To access this document go to ni com info and enter the info code rdfwin PCI Local Bus Specification Revision 2 1 National Instruments PXI Specification Revision 1 0 PICMG 2 0 R2 1 CompactPCI Software documentation Examples of software documentation you may have are the LabVIEW or LabWindows CVI documentation sets and the NI DAQmx or Tra...

Page 10: ...ips control the 96 bits of TTL compatible digital I O on the PCI DIO 96 or PXI 6508 On the PCI 6503 one 82C55A PPI controls the 24 bits of TTL compatible digital I O The 82C55A PPI chips can operate in unidirectional mode bidirectional mode or handshaking mode and can generate interrupt requests to your computer The digital I O lines are all accessible through a 100 pin female connector on the PCI...

Page 11: ...I bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses Your PXI 6508 device works in any standard CompactPCI chassis adhering to the PICMG 2 0 R2 1 CompactPCI core specification What You Need to Get Started To set up and use you...

Page 12: ...uipment available from National Instruments visit ni com Custom Cabling Caution For compliance with Electromagnetic Compatibility EMC requirements this product must be operated with shielded cables and accessories If unshielded cables or accessories are used the EMC specifications are no longer guaranteed unless all unshielded cables and or accessories are installed in a shielded enclosure with pr...

Page 13: ...IO board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your computer chassis before removing the board fro...

Page 14: ...ns for installing software and hardware configuring channels and tasks and getting started developing an application Installing Other Software If you are using other software refer to the installation instructions that accompany your software Hardware Installation The following sections contain general installation instructions for each device Consult your computer or chassis user manual or techni...

Page 15: ...r CompactPCI 5 V peripheral slot 3 Remove the filler panel for the peripheral slot you have chosen 4 Touch a metal part of your chassis to discharge any static electricity that might be on your clothes or body 5 Insert the PXI 6508 in the selected 5 V slot Use the injector ejector handle to fully inject the device into place 6 Screw the front panel of the PXI 6508 to the front panel mounting rails...

Page 16: ...s chapter includes information about maximum input ratings National Instruments is not liable for any damages resulting from signal connections that exceed these maximum ratings Note For information on adding signal conditioning into your applications and National Instruments signal conditioning devices go to ni com signalconditioning I O Connector PCI DIO 96 PXI 6508 The I O connector for the PCI...

Page 17: ... APC5 BPC6 APC6 BPC7 APC7 GND 5 V DPA0 CPA0 DPA1 CPA1 DPA2 CPA2 DPA3 CPA3 DPA4 CPA4 DPA5 CPA5 DPA6 CPA6 DPA7 CPA7 DPB0 CPB0 DPB1 CPB1 DPB2 CPB2 DPB3 CPB3 DPB4 CPB4 DPB5 CPB5 DPB6 CPB6 DPB7 CPB7 DPC0 CPC0 DPC1 CPC1 DPC2 CPC2 DPC3 CPC3 DPC4 CPC4 DPC5 CPC5 DPC6 CPC6 DPC7 CPC7 51 1 52 2 53 3 54 4 55 5 56 6 57 7 58 8 59 9 60 10 61 11 62 12 63 13 64 14 65 15 66 16 67 17 68 18 69 19 70 20 71 21 72 22 73 ...

Page 18: ...ors on the cable assembly Figure 3 2 Cable Assembly Connector Pinout for the R1005050 Ribbon Cable PCI DIO 96 and PXI 6508 5 V APA0 APA1 APA2 APA3 APA4 APA5 APA6 APA7 APB0 APB1 APB2 APB3 APB4 APB5 APB6 APB7 APC0 APC1 APC2 APC3 APC4 APC5 APC6 APC7 GND BPA1 BPA2 BPA4 BPA5 BPA6 BPA7 BPA0 BPA3 BPB0 BPB1 BPB2 BPB3 BPB4 BPB5 BPB6 BPB7 BPC0 BPC1 BPC2 BPC3 BPC4 BPC5 BPC6 BPC7 49 50 47 48 45 46 43 44 41 42...

Page 19: ...ional data lines for port B of PPI A APB7 is the MSB APB0 is the LSB 18 20 22 24 26 28 30 32 BPB 7 0 4 Bidirectional data lines for port B of PPI B BPB7 is the MSB BPB0 is the LSB 33 35 37 39 41 43 45 47 APA 7 0 0 Bidirectional data lines for port A of PPI A APA7 is the MSB APA0 is the LSB 34 36 38 40 42 44 46 48 BPA 7 0 3 Bidirectional data lines for port A of PPI B BPA7 is the MSB BPA0 is the LS...

Page 20: ...data lines for port A of PPI D DPA7 is the MSB DPA0 is the LSB This document refers to the ports as A B and C and the PPIs 82C55As as A B C and D NI DAQmx Traditional NI DAQ Legacy and LabVIEW documentation use numbers to identify each port and PPI For example this manual uses PPI A port A to refer to port A of the 82C55A identified as PPI A NI DAQmx Traditional NI DAQ Legacy LabWindows CVI LabVIE...

Page 21: ...nments for the PCI 6503 digital I O connector using the NB1 ribbon cable Figure 3 3 PCI 6503 I O Connector Pin Assignments 5 V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26...

Page 22: ...gnal Descriptions Pin Signal Name Alternate Port ID Description 1 3 5 7 9 11 13 15 PC 7 0 2 Port C Bidirectional data lines for port C PC7 is the MSB PC0 is the LSB 17 19 21 23 25 27 29 31 PB 7 0 1 Port B Bidirectional data lines for port B PB7 is the MSB PB0 is the LSB 33 35 37 39 41 43 45 47 PA 7 0 0 Port A Bidirectional data lines for port B PA7 is the MSB PA0 is the LSB 49 5 V 5 Volts This pin...

Page 23: ...input logic high and output logic high voltages assume a Vcc supply voltage of 5 0 V The absolute maximum voltage rating is 0 5 to 5 5 V with respect to GND For more information on the digital I O signal specifications refer to Appendix A Specifications Table 3 3 Port C Signal Assignments Configuration Terminology Signal Assignments 82C55A PCI DIO 96 PXI 6508 PCI 6503 User Manual National Instrume...

Page 24: ...f one PPI is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 3 4 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3 4 41 43 45 47 67 69 71 73 50 100 GND Switch I O Connector...

Page 25: ...ine is configured as an input pulled either high or low by a 100 kΩ bias resistor On the PCI DIO 96 all of the 100 kΩ bias resistors pull up Therefore the default power up state of each line on the PCI DIO 96 is high On the PXI 6508 and PCI 6503 you can select the direction of the 100 kΩ bias resistors Set jumper W1 to high to configure the resistors as pull up resistors Set jumper W1 to low to co...

Page 26: ...e the largest possible load to maintain a logic low level of 0 4 V and supply the maximum driving current V I RL RL V I where V 0 4 V Voltage across RL I 46 μA 10 μA 4 6 V across the 100 kΩ pull up resistor and 10 μA maximum leakage current except lines PC0 and PC3 therefore RL 7 1 kΩ 0 4 V 56 μA This resistor value 7 1 kΩ provides a maximum of 0 4 V on the DIO line at power up You can substitute ...

Page 27: ...with the current from the 100 kΩ pull down resistor brings the voltage at the resistor below a TTL high level of 2 8 VDC Figure 3 6 DIO Channel Configured for Low DIO Power up State with External Load Example Set jumper W1 to low which means all DIO lines are pulled low at power up To pull one channel high complete the following steps 1 Install a load RL Remember that the smaller the resistance th...

Page 28: ... on the DIO line at power up You can substitute smaller resistor values to lower the voltage drop or to provide a margin for VCC variations and other factors However smaller values draw more current leaving less sink current for other circuitry connected to this line The 5 7 kΩ resistor reduces the amount of a logic low sink current by 0 8 mA with a 0 4 V output ...

Page 29: ...anual 4 Theory of Operation This chapter contains a functional overview of the PCI DIO 96 PXI 6508 and PCI 6503 and explains the operation of each functional unit Functional Overview The block diagram in Figure 4 1 illustrates the key functional components of your DIO board ...

Page 30: ...D or earlier refer to Appendix B Register Level Programming for more information about using the 82C53 I O Connector Interrupt Control Circuitry Port A Port B Port C Port A Port B Port C Port A Port B Port C Port A Port B Port C 8 8 8 8 8 8 8 8 8 8 8 8 PCI MITE Interface Circuitry Interrupt 1 Data Bus Interrupt Bus Interrupt PCI or PXI 1 A Fuse 5 VDC System 2 Arbitration 2 Error Reporting 2 Interf...

Page 31: ...e 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits plus control and status bits from port C PC Modes 1 and 2 use handshaking signals from the computer to synchronize data transfers Refer to Appendix B Register Level Programming for more detailed information Different revisions of the PCI DIO 96 PXI 6508 and PCI 6503 use different 82C...

Page 32: ...edge Input A low signal on this handshaking line indicates that the data written to the port has been accepted This signal is a response from the external device indicating that it has received the data from your DIO board OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written to the port INTR Output Interrupt Request This signal becomes high when ...

Page 33: ...tions for an input transfer in mode 1 Figure 4 2 Timing Specifications for Mode 1 Input Transfer Name Description Minimum Maximum T1 STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 ...

Page 34: ...ations for an output transfer in mode 1 Figure 4 3 Timing Specifications for Mode 1 Output Transfer Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 ...

Page 35: ... 4 Timing Specifications for Mode 2 Bidirectional Transfer Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OB...

Page 36: ...4 I O Compatibility TTL Power on state PCI DIO 96 Inputs high Z pulled up through 100 kΩ PXI 6508 PCI 6503 Inputs high Z pulled up or down through 100 kΩ jumper selectable Handshaking Input output or bidirectional Data transfers Interrupts programmed I O Digital Logic Levels Input Signals The maximum input logic high and output logic high voltages assume a Vcc supply voltage of 5 0 V Given a Vcc s...

Page 37: ...n Arrays to increase the current drive of digital output lines For more information about the breakdown levels of your device and for a link to the 82C55 data sheets refer to ni com info and enter the info code 82c55 Level Min Max Input logic high voltage 2 2 V 5 3 V Input logic low voltage 0 3 V 0 8 V Input high current Vin 5 V resistors set to pull up 10 μA Input high current Vin 5 V resistors s...

Page 38: ...age and code efficiency Execution mode foreground or background with background execution typically using interrupts Other operations in progress Application For example you can obtain higher transfer rates in a handshaking or data transfer application requiring an average rate than in a pattern generation data acquisition or waveform generation application requiring a constant sustainable rate Th...

Page 39: ...6 101 g 3 6 oz PXI 6508 148 g 5 2 oz PCI 6503 55 g 1 9 oz I O connector PCI DIO 96 and PXI 6508 100 pin female 0 050 series D type PCI 6503 50 pin male ribbon cable connector Environment If you need to clean the module use a soft non metallic brush Operating temperature 0 to 55 C Storage temperature 20 to 70 C Relative humidity 5 to 90 noncondensing Maximum altitude 2 000 meters Pollution Degree 2...

Page 40: ...6508 PCI 6503 meets the requirements of the following standards of safety for electrical equipment for measurement control and laboratory use IEC 61010 1 EN 61010 1 UL 61010 1 CSA 61010 1 Note For UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards ...

Page 41: ...ible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers For additional environmental information refer to the NI and the Environment Web page at ni com environment This page contains the environmental regulations and directives with which NI complies as well as other environmental information not included in thi...

Page 42: ...nt Studio for Visual Studio NET or LabWindows CVI to program your NI PCI DIO 96 PXI 6508 and PCI 6503 device for improved productivity NI DAQmx and Traditional NI DAQ Legacy software provides easier programming with the same flexibility as register level programming NI DAQmx and Traditional NI DAQ Legacy driver software will not work for your programming needs in some cases however For example if ...

Page 43: ...ailed information Interrupt Control Circuitry Two software controlled registers determine which devices if any generate interrupts Each of the 82C55A devices has two interrupt lines PC3 and PC0 connected to the interrupt circuitry On the PCI DIO 96 and PXI 6508 the 82C53 device has two of its three counter outputs connected to the interrupt circuitry Any of these 10 signals can interrupt the compu...

Page 44: ...ock diagram in Figure B 1 illustrates the interrupt control circuitry Figure B 1 Interrupt Control Circuitry Block Diagram CLK0 GATE0 OUT0 CLK1 GATE1 OUT1 CLK2 GATE2 OUT2 2 MHz 5 V 5 V 82C55A PPI A 82C55A PPI B 82C55A PPI D 82C55A PPI C PCI Interrupt PC3 PC0 PC3 PC0 PC3 PC0 82C53 Counter Timer PC3 PC0 Interrupt Control Circuitry Interrupt Control Registers PCI DIO 96 PXI 6508 Only ...

Page 45: ...6508 they are referenced as PPI A PPI B PPI C and PPI D On the PCI DIO 96 and PXI 6508 the three 16 bit counters of the 82C53 are accessed through individual data ports and controlled by one 8 bit control word The control word selects how the counter data ports are accessed and what mode the counter uses The Register Description for the 82C53 PCI DIO 96 PXI 6508 Only section contains definitions f...

Page 46: ...ster Group Continued PPI B PORTA Register PORTB Register PORTC Register Configuration Register 04 05 06 07 8 bit 8 bit 8 bit 8 bit Read and write Read and write Read and write Write only No No No No PPI C PORTA Register PORTB Register PORTC Register Configuration Register 08 09 0A 0B 8 bit 8 bit 8 bit 8 bit Read and write Read and write Read and write Write only No No No No PPI D PORTA Register PO...

Page 47: ...scription of each bit The register bit map shows a diagram of the register with the MSB bit 7 shown on the left and the LSB bit 0 shown on the right A rectangle with the bit name inside represents each bit The bit map for the Interrupt Clear Register states not applicable no bits used The data is ignored when you write to this register therefore any bit pattern is sufficient Register Description f...

Page 48: ...up B Mode Selection 00 Mode 0 01 Mode 1 1X Mode 2 Control Word Flag 1 Mode Set Port A 1 Input 0 Output Port C high nibble 1 Input 0 Output Port C low nibble 1 Input 0 Output Port B 1 Input 0 Output Mode Selection 0 Mode 0 1 Mode 1 a Control Word Flag Mode Set bit 7 1 D7 D6 D5 D4 D3 D2 D1 D0 Control Word Flag 0 Bit Set Reset Unused Bit Set Reset 1 Set 0 Reset Bit Select 000 001 010 111 b Control Wo...

Page 49: ...set reset option for the bits of port C clears bit 7 of the control word Table B 2 Port C Set Reset Control Words Bit Number Bit Set Control Word Bit Reset Control Word Bit Set or Reset in Port C 0 0xxx0001 0xxx0000 xxxxxxxb 1 0xxx0011 0xxx0010 xxxxxxbx 2 0xxx0101 0xxx0100 xxxxxbxx 3 0xxx0111 0xxx0110 xxxxbxxx 4 0xxx1001 0xxx1000 xxxbxxxx 5 0xxx1011 0xxx1010 xxbxxxxx 6 0xxx1101 0xxx1100 xbxxxxxx 7...

Page 50: ...ts 3 2 and 1 select the mode for the selected counter Bit 0 selects whether the counter counts in binary or BCD format After writing to the Configuration Register to configure a counter you can read or write the counter itself eight bits at a time as controlled by the access mode Figure B 3 Control Word Format for the 82C53 D7 D6 D5 D4 D3 D2 D1 D0 Counter Select 00 Counter 0 01 Counter 1 10 Counte...

Page 51: ...Register 1 Address Base address 14 hex Type Write only Word Size 8 bit Bit Map PCI DIO 96 PXI 6508 Bit Map PCI 6503 Bit Name Description 7 2 X Reserved on the PCI 6503 7 DIRQ1 PPI D Port B Interrupt Enable Bit If this bit and the INTEN bit in Interrupt Control Register 2 are both set PPI D sends an interrupt INTRB to the computer If this bit is cleared PPI D does not send the interrupt INTRB to th...

Page 52: ...are both set PPI B sends an interrupt INTRB to the computer If this bit is cleared PPI B does not send the interrupt INTRB to the computer regardless of the setting of INTEN 2 BIRQ0 PPI B Port A Interrupt Enable Bit If this bit and the INTEN bit in Interrupt Control Register 2 are both set PPI B sends an interrupt INTRA to the computer If this bit is cleared PPI B does not send the interrupt INTRA...

Page 53: ...is bit is set the 82C53 counter outputs can interrupt the computer If this bit is cleared the counter outputs have no effect To avoid a spurious interrupt keep INTEN low when you set CTRIRQ that is set CTRIRQ before setting INTEN 0 CTR1 Counter Select Bit If this bit is set the output from counter 1 of the 82C53 is connected to the interrupt request circuitry In this mode counter 0 of the 82C53 ac...

Page 54: ...Only The interrupt clear register has no bits associated with it Use this register to reset the state of the interrupt request signal once the interrupt routine has been entered To clear the interrupt perform an 8 bit write to this register address the data is irrelevant Address Base address 16 hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 0 X Don t care bit 7 6 5 4 3 2 1 0 X ...

Page 55: ... All three boards use the PCI Local Bus to move data The PCI Local Bus is a high performance 32 bit bus with multiplexed address and data lines The PCI system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers Bus related resources must be configured before you attempt to execute a register level program This entails assigning a base address an...

Page 56: ...ation space for the National Instruments vendor ID 0x1093 and PCI DIO 96 device ID 0x0160 PXI 6508 device ID 0x13c0 or PCI 6503 device ID 0x17d0 If a board is found the algorithm can store all the board s configuration information into a data structure Table B 3 Common Programming Example Terms Term Definition Port A Address of PPI A Port A Register Base Address 0x00 Port B Address of PPI A Port B...

Page 57: ...o PCI configuration space offset 0x10 BAR0 2 Write the value 0x0000aeae to offset 0x340 from the new PCI MITE address 3 Write the address to which you want to re map the board other than the PCI MITE to PCI configuration space offset 0x14 BAR1 4 Create the window data value by masking the new board address window data value 0xffffff00 and new board address or 0x00000080 If you are not remapping th...

Page 58: ...and group B and includes the following features Each group contains one 8 bit data port port A or port B and one 3 bit control data port upper or lower portion of port C The 8 bit data ports can be either input or output both are latched The 3 bit ports are used for control and status of the 8 bit data ports Interrupt generation and enable disable functions are available Mode 2 Bidirectional bus T...

Page 59: ... B Port A Port C Port B Port C 0 10000000 Output Output Output Output 1 10000001 Output Output Output Input 2 10000010 Output Output Input Output 3 10000011 Output Output Input Input 4 10001000 Output Input Output Output 5 10001001 Output Input Output Input 6 10001010 Output Input Input Output 7 10001011 Output Input Input Input 8 10010000 Input Output Output Output 9 10010001 Input Output Output ...

Page 60: ...onfigure the don t care bits appropriately in the control word if you want to use the other ports in combination with the example In mode 1 the digital I O bits are divided into two groups group A and group B Each of these groups contains one 8 bit port and one 3 bit control data port The 8 bit port can be either an input or an output port and the 3 bit port is used for control and status informat...

Page 61: ...re both enabled for handshaking Figure B 5 Control Word to Configure Port B for Mode 1 Input During a mode 1 data read transfer read port C to obtain the status of the handshaking lines and interrupt signals Refer to the Port C Status Word Bit Definitions for Input Ports A and B section the Port C Status Word Bit Definitions for Output Ports A and B section and the Port C Status Word Bit Definitio...

Page 62: ...g indicates that data has been loaded into the input latch for port A 4 INTEA Interrupt Enable Bit for Port A Setting this bit enables the INTRA flag from port A of the 82C55A Control INTEA by setting resetting PC4 3 INTRA Interrupt Request Status for Port A This status flag which operates only when INTEA is high indicates that port A has acquired data and is ready to be read If you have enabled i...

Page 63: ... connector port C has the pin assignments shown in Figure B 6 when in mode 1 input Notice that the status of STBA and the status of STBB are not included in the port C status word Figure B 6 Port C Pin Assignments on I O Connector when Port C Configured for Mode 1 Input Mode 1 Strobed Input Programming Example The following example shows how to configure PPI A for mode 1 input Write 8255Cnfg 0xB0 ...

Page 64: ...ra input or output lines Figure B 7 Control Word to Configure Port A for Mode 1 Output Figure B 8 shows the control word written to the Configuration Register to configure port B for output in mode 1 Notice that port B does not have extra input or output lines left from port C when ports A and B are both configured for handshaking Figure B 8 Control Word to Configure Port B for Mode 1 Output Durin...

Page 65: ... I O Input Output These bits can be used for general purpose I O when port A is in mode 1 output If these bits are configured for output you must use the port C bit set reset function to manipulate them 3 INTRA Interrupt Request Status for Port A This status flag which operates only when INTEA is high indicates that port A has acquired data and is ready to be read If you have enabled interrupts by...

Page 66: ...onnector port C has the pin assignments shown in Figure B 9 when in mode 1 output Notice that the status of ACKA and ACKB are not included when port C is read Figure B 9 Port C Pin Assignments on I O Connector when Port C Configured for Mode 1 Output Mode 1 Strobed Output Programming Example The following example shows how to configure PPI A for mode 1 output Write 8255Cnfg 0xA0 Set mode 1 port A ...

Page 67: ...wever port B can be used in either mode 0 or mode 1 while port A is configured for mode 2 Figure B 10 shows the control word written to the Configuration Register to configure port A as a bidirectional data bus in mode 2 If port B is configured for mode 0 you can use PC2 PC1 and PC0 of port C as extra input or output lines Figure B 10 Control Word to Configure Port A as Mode 2 Bidirectional Data B...

Page 68: ...Input Buffer Full for Port A A high setting indicates that data has been loaded into the input latch of port A 4 INTE2 Interrupt Enable Bit for Port A Input Interrupts Setting this bit enables the INTRA flag from port A of the 82C55A for input Control this bit by setting resetting PC4 3 INTRA Interrupt Request Status for Port A This status flag which operates only when INTE1 or INTE2 is high indic...

Page 69: ...g 0xC0 Set mode 2 port A is bidirectional Write 8255Cnfg 0x09 Set PC4 to enable the INTRA status flag for input Write 8255Cnfg 0x0D Set PC6 to enable the INTRA status flag for output Loop until the INTRA PC3 status flag is set indicating the 82C55 is ready for a transfer If IBFA PC5 is set read PortA If input buffer is full read data If OBFA PC7 is set write PortA data If output buffer is not full...

Page 70: ...generate interrupts when port A or port B is in mode 0 and the low nibble of port C is configured for input If port A is in mode 0 use PC3 to generate an interrupt if port B is in mode 0 use PC0 to generate an interrupt After you have configured the selected 82C55A you must set the corresponding interrupt enable bit in Interrupt Control Register 1 If you are using PC3 set xIRQ0 if you are using PC...

Page 71: ...0 Set mode 2 port A is bidirectional Write 8255Cnfg 0x09 Set PC4 to enable interrupt from 82C55A Write IREG2 0x04 Set INTEN bit Write IREG1 0x01 Set AIRQ0 to enable PPI A port A interrupts Programming Considerations for the 82C53 The PCI DIO 96 and PXI 6508 contain an 82C53 programmable interval timer The following section contains a general overview and configuration information for the 82C53 Gen...

Page 72: ... 0x00 Disable counter interrupts Write CntrCnfg 0x34 Set counter 0 to mode 2 Write IREG2 0x02 Enable counter interrupts and select the output from counter 0 before enabling board interrupts Write IREG2 0x06 Enable board interrupts Write Ctr0 Data0 Send the least significant byte of the counter data to counter 0 Write Ctr0 Data1 Send the most significant byte of the counter data to counter 0 The co...

Page 73: ... Standard Service Program Membership This program entitles members to direct access to NI Applications Engineers via phone and email for one to one technical support as well as exclusive access to on demand training modules via the Services Resource Center NI offers complementary membership for a full year after purchase after which you may renew to continue your benefits For information about oth...

Page 74: ...our product by visiting ni com certification Calibration Certificate If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can vi...

Page 75: ...y Symbol Prefix Value n nano 10 9 μ micro 10 6 m milli 10 3 k kilo 103 M mega 106 Numbers Symbols degrees greater than greater than or equal to less than negative of or minus Ω ohms per percent plus or minus positive of or plus 5 V 5 Volts signal A A amperes ACK acknowledge input signal ...

Page 76: ...tion Specific Integrated Circuit AWG American Wire Gauge B BCD binary coded decimal BIRQ0 PPI B port A interrupt enable bit BIRQ1 PPI B port B interrupt enable bit BPA PPI B port A BPB PPI B port B BPC PPI B port C C C Celsius CIRQ0 PPI C port A interrupt enable bit CIRQ1 PPI C port B interrupt enable bit cm centimeters CompactPCI refers to the core specification defined by the PCI Industrial Comp...

Page 77: ...l signals DI digital input DIO digital input output DIRQ0 PPI D port A interrupt enable bit DIRQ1 PPI D port B interrupt enable bit DMA direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory DO digital output DPA PPI D ...

Page 78: ... output interrupt enable bit INTE2 port A input interrupt enable bit INTEA port A interrupt enable bit INTEB port B interrupt enable bit INTEN interrupt enable bit INTRA port A interrupt request status INTRB port B interrupt request status L LED light emitting diode LSB least significant bit M m meters max maximum MB megabytes of memory min minutes ...

Page 79: ...ffers a theoretical maximum transfer rate of 132 Mbytes s port a digital port consisting of four or eight lines of digital input and or output PPI programmable peripheral interface PXI PCI eXtensions for Instrumentation PXI is an open specification that builds off the CompactPCI specification by adding instrumentation specific features R RD read signal S S samples s seconds SCXI Signal Conditionin...

Page 80: ...TL transistor transistor logic typ typical V V volts Vcc supply voltage for example the voltage a computer supplies to its plug in devices VDC volts direct current VI virtual instrument a combination of hardware and or software elements typically used with a PC that has the functionality of a classic standalone instrument Vin input voltage W W watts WRT write signal ...

Page 81: ... of operation 4 3 programming considerations B 17 mode 1 strobed input B 19 programming example B 22 mode 1 strobed output B 23 programming example B 25 mode 2 bidirectional bus B 26 programming example B 28 modes of operation B 17 mode 0 basic I O B 18 register group control word formats figure B 7 description B 6 port C set reset control words table B 8 status word bit definitions for bidirectio...

Page 82: ... PXI compatible products 1 2 configuration 2 1 board configuration 2 2 connections power 3 10 connectors cable assembly 3 3 control words 82C53 register group format figure B 9 82C55A register group formats figure B 7 port C set reset table B 8 mode 1 strobed input port A configuration figure B 19 port B configuration figure B 20 mode 1 strobed output port A configuration figure B 23 port B config...

Page 83: ...10 figure 3 11 I I O bit mode 1 strobed input description B 21 mode 1 strobed output description B 24 mode 2 bidirectional bus description B 27 I O connector cable assembly connector pinouts figure pins 1 through 50 3 3 exceeding maximum ratings caution 3 1 PCI 6503 3 6 pin assignments PCI 6503 figure 3 6 PCI DIO 96 and PXI 6508 figure 3 2 port C pin assignments mode 1 input figure B 22 mode 1 out...

Page 84: ... strobed output description B 25 K KnowledgeBase C 1 L low DIO power up state 3 12 figure 3 12 M MITE ASIC See PCI MITE ASIC mode 0 basic I O I O configurations table B 18 programming considerations B 17 programming example B 19 mode 1 input interrupt programming example B 29 strobed I O programming considerations B 17 control word to configure port A figure B 19 control word to configure port B f...

Page 85: ... 13 unpacking 1 4 PCI DIO 96 and PXI 6508 connector pin assignments figure 3 2 I O connector 3 1 signal cable descriptions table 3 4 PCI DIO 96 PCI 6503 hardware installation 2 1 PCI DIO 96 PXI 6508 PCI 6503 board block diagram figure 4 2 configuration 2 2 custom cabling 1 3 optional equipment 1 3 overview 1 1 requirements for getting started 1 2 unpacking 1 4 physical specifications A 4 pin assig...

Page 86: ...er level programming B 1 B 14 82C55A modes of operation B 17 examples B 14 B 29 interrupt handling 82C53 B 31 mode 1 strobed input B 29 mode 1 strobed output B 30 mode 2 bidirectional bus B 30 mode 0 basic I O B 19 mode 1 strobed input B 22 mode 1 strobed output B 25 mode 2 bidirectional bus B 28 PCI initialization B 15 interrupt handling B 29 programming examples 82C53 B 31 82C55A B 29 mode 0 bas...

Page 87: ...sembly connector pinouts pins 1 through 50 figure 3 3 PCI 6503 connector pin assignments figure 3 6 PCI DIO 96 and PXI 6508 connector pin assignments figure 3 2 power connections 3 10 signal descriptions PCI 6503 table 3 7 PCI DIO 96 and PXI 6508 pin assignments table 3 4 timing specifications 4 4 mode 1 input timing 4 5 mode 1 output timing 4 6 mode 2 bidirectional timing 4 7 signal names used in...

Page 88: ...de 1 input timing 4 5 mode 1 output timing 4 6 mode 2 bidirectional timing 4 7 signal names used in timing diagrams table 4 4 training and certification NI resources C 1 transfer rates specifications A 3 troubleshooting NI resources C 1 W Web resources C 1 WR signal description table 4 4 ...

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